Rtc Time-Stamp Sub Second Register (Rtc_Tsssr) - ST STM32L4x6 Reference Manual

RM0351
34.6.14

RTC time-stamp sub second register (RTC_TSSSR)

The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 SS: Sub second value
SS[15:0] is the value of the synchronous prescaler counter when the timestamp event
occurred.
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
DocID024597 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
SS[15:0]
r r r r
Real-time clock (RTC)
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
r r r r
1097/1693
16
Res.
0
r
1106