Control Register 2 (Usartx_Cr2) - ST STM32L4x6 Reference Manual

RM0351
Bit 2 RE: Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 UESM: USART enable in Stop mode
When this bit is cleared, the USART is not able to wake up the MCU from Stop mode.
When this bit is set, the USART is able to wake up the MCU from Stop mode, provided that
the USART clock selection is HSI16 or LSE in the RCC.
This bit is set and cleared by software.
0: USART not able to wake up the MCU from Stop mode.
1: USART able to wake up the MCU from Stop mode. When this function is active, the clock
source for the USART must be HSI16 or LSE (see
(RCC)
Note: It is recommended to set the UESM bit just before entering Stop mode and clear it on
Bit 0 UE: USART enable
When this bit is cleared, the USART prescalers and outputs are stopped immediately, and
current operations are discarded. The configuration of the USART is kept, but all the status
flags, in the USARTx_ISR are set to their default values. This bit is set and cleared by
software.
0: USART prescaler and outputs disabled, low-power mode
1: USART enabled
Note: In order to go into low-power mode without generating errors on the line, the TE bit
36.8.2

Control register 2 (USARTx_CR2)

Address offset: 0x04
Reset value: 0x0000
31 30 29
ADD[7:4]
rw rw rw
15 14 13
SWAP LINEN STOP[1:0]
rw rw rw
Universal synchronous asynchronous receiver transmitter (USART)
.
exit from Stop mode.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
forced by hardware to '0'. Please refer to
page 1180.
must be reset before and the software must wait for the TC bit in the USARTx_ISR to
be set before resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.
28 27 26 25
ADD[3:0]
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12 11 10 9
CLKEN CPOL CPHA
rw rw rw rw
Section 36.4: USART implementation on
24 23 22
RTOEN ABRMOD[1:0]
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8 7 6
LBCL Res. LBDIE
rw rw
DocID024597 Rev 3
Section Reset and clock control
21 20 19 18
MSBFI
ABREN DATAINV TXINV
RST
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5 4 3
LBDL ADDM7 Res. Res.
rw rw
17 16
RXINV
rw rw
2 1 0
Res. Res.
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