Figure 454. Swpmi Block Diagram; Swpmi Functional Description - ST STM32L4x6 Reference Manual

RM0351
40.3

SWPMI functional description

40.3.1 SWPMI block diagram
Refer to the bit SWPMI1SEL in
register (RCC_CCIPR)
Note: In order to support the exit from Stop mode by a RESUME by slave, it is mandatory to select
HSI16 for SWPCLK. If this feature is not required, PCLK1 can be selected, and SWPMI
must be disabled before entering the Stop mode.
40.3.2 SWP initialization and activation
The initialization and activation will set the SWPMI_IO state from low to high. The procedure
is the following:
1. configure the SWP_CLASS bit in SWPMI_OR register according to the V
(3 V or 1.8 V),
2. configure SWPMI_IO as alternate function (refer to
(GPIO)) to enable the SWPMI_IO transceiver,
3. wait for at least 20 microseconds,
4. set SWPACT bit in SWPMI_CR register to ACTIVATE the SWP i.e. to move from
DEACTIVATED to SUSPENDED.
40.3.3 SWP bus states
The SWP bus can have the following states: DEACTIVATED, SUSPENDED, ACTIVATED.
Single Wire Protocol Master Interface (SWPMI)

Figure 454. SWPMI block diagram

Section 6.4.28: Peripherals independent clock configuration
to select the SWPCLK (SWPMI core clock source).
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Section 7: General-purpose I/Os
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