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RM0351
44.16.5
Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
Address: 0xE004 200C
Power on reset (POR): 0x0000 0000
System reset: not affected
Access: Only 32-bit access are supported.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 DBG_LPTIM2_STOP: LPTIM2 counter stopped when core is halted
0: The counter clock of LPTIM2 is fed even if the core is halted
1: The counter clock of LPTIM2 is stopped when the core is halted
Bits 4:0 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
DocID024597 Rev 3
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
DBG_
Res.
Res.
Res.
LPTIM2
_STOP
rw
Debug support (DBG)
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
Res.
1669/1693
16
Res.
0
Res.
1678
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