Figure 456. Swp Frame Structure; Transmission Procedure - ST STM32L4x6 Reference Manual

Single Wire Protocol Master Interface (SWPMI)
The SWPMI embeds one 32-bit data register for transmission (SWPMI_TDR), and one 32-
bit data register for reception (SWPMI_RDR).
In transmission, the SOF insertion, the CRC calculation and insertion, and the EOF
insertion are managed automatically by the SWPMI. The user only has to provide the
Payload content and size. A frame transmission starts as soon as data is written into the
SWPMI_TDR register. Dedicated flags indicate an empty transmit data register and a
complete frame transmission event.
In reception, the SOF deletion, the CRC calculation and checking, and the EOF deletion are
managed automatically by the SWPMI. The user only has to read the Payload content and
size. Dedicated flags indicate a full receive data register, a complete frame reception and
possibly CRC error events.
The stuffing bits insertion (in transmission) and stuffing bits deletion (in reception) are
managed automatically by the SWPMI core. These operations are transparent for the user.
40.3.7

Transmission procedure

Before starting any frame transmission, the user must activate the SWP. Refer to
Section 40.3.2: SWP initialization and
There are several possible software implementations for a frame transmission: No software
buffer mode, Single software buffer mode, and Multi software buffer mode.
The software buffer usage requires the use of a DMA channel to transfer data from the
software buffer in the RAM memory to the transmit data register in the SWPMI peripheral.
No software buffer mode
This mode does not require the use of DMA. The SWP frame transmission handling is done
by polling status flags in the main loop or inside the SWPMI interrupt routine. There is a 32-
bit transmit data register (SWPMI_TDR) in the SWPMI, thus writing to this register will
trigger the transmission of up to 4 bytes.
The No software buffer mode is selected by clearing TXDMA bit in the SWPMI_CR register.
The frame transmission is started by the first write to the SWPMI_TDR register. The low
significant byte of the first 32-bit word (bits [7:0])written into the SWPMI_TDR register)
indicates the number of data bytes in the payload, and the 3 other bytes of this word must
contain the first 3 bytes of the payload (bits [15:8] contain the first byte of the payload, bits
[23:16] the second byte and bits [31:24] the third byte). Then, the following writes to the
SWPMI_TDR register will only contain the following payload data bytes, up to 4 for each
write.
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Figure 456. SWP frame structure

activation.
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