Rtc Control Register (Rtc_Cr) - ST STM32L4x6 Reference Manual

RM0351
34.6.3

RTC control register (RTC_CR)

Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
TSIE WUTIE ALRBIE ALRAIE
rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 ITSE: timestamp on internal event enable
Bit 23 COE: Calibration output enable
This bit enables the RTC_CALIB output
Bits 22:21 OSEL[1:0]: Output selection
These bits are used to select the flag to be routed to RTC_ALARM output
Bit 20 POL: Output polarity
This bit is used to configure the polarity of RTC_ALARM output
Bit 19 COSEL: Calibration output selection
When COE=1, this bit selects which signal is output on RTC_CALIB.
These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values
(PREDIV_A=127 and PREDIV_S=255). Refer to
Bit 18 BKP: Backup
This bit can be written by the user to memorize whether the daylight saving time change has
been performed or not.
Bit 17 SUB1H: Subtract 1 hour (winter time change)
When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the
current hour is not 0. This bit is always read as 0.
Setting this bit has no effect when current hour is 0.
28 27 26 25
Res. Res. Res.
12 11 10 9
TSE WUTE ALRBE ALRAE
rw rw rw rw
0: internal event timestamp disabled
1: internal event timestamp enabled
0: Calibration output disabled
1: Calibration output enabled
00: Output disabled
01: Alarm A output enabled
10: Alarm B output enabled
11: Wakeup output enabled
0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).
0: Calibration output is 512 Hz
1: Calibration output is 1 Hz
0: No effect
1: Subtracts 1 hour to the current time. This can be used for winter time change.
24 23 22
ITSE COE OSEL[1:0]
rw rw rw
8 7 6
Res. FMT
rw rw
Section 34.3.15: Calibration clock output
DocID024597 Rev 3
Real-time clock (RTC)
21 20 19
POL COSEL
rw rw rw
5 4 3
BYPS
REFCKON TSEDGE
HAD
rw rw rw
18 17 16
BKP SUB1H ADD1H
rw w w
2 1 0
WUCKSEL[2:0]
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