Figure 382. I2C Interrupt Mapping Diagram; I2C Registers - ST STM32L4x6 Reference Manual

Inter-integrated circuit (I2C) interface
35.7

I2C registers

Refer to
The peripheral registers are accessed by words (32-bit).
35.7.1 Control register 1 (I2C_CR1)
Address offset: 0x00
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.
31 30 29
Res. Res. Res.
15 14 13
RXDMA TXDMA
Res.
EN EN
rw rw
Bits 31:24 Reserved, must be kept at reset value.
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Figure 382. I2C interrupt mapping diagram

Section 1.1 on page 61
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
ANF
DNF
OFF
rw rw
for a list of abbreviations used in register descriptions.
24 23 22
ALERT
Res. PECEN
EN
rw rw
8 7 6
ERRIE TCIE
rw rw
DocID024597 Rev 3
21 20 19 18
SMBD SMBH WUPE
GCEN
EN EN N
rw rw rw
5 4 3 2
STOP NACK ADDR
RXIE
IE IE IE
rw rw rw rw
RM0351
17 16
NOSTR
SBC
ETCH
rw rw
1 0
TXIE PE
rw rw