Can Registers - ST STM32L4x6 Reference Manual

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Controller area network (bxCAN)
The FIFO 1 interrupt can be generated by the following events:
The error and status change interrupt can be generated by the following events:
42.9

CAN registers

The peripheral registers have to be accessed by words (32 bits).
42.9.1
Register access protection
Erroneous access to certain configuration registers can cause the hardware to temporarily
disturb the whole CAN network. Therefore the CAN_BTR register can be modified by
software only while the CAN hardware is in initialization mode.
Although the transmission of incorrect data will not cause problems at the CAN network
level, it can severely disturb the application. A transmit mailbox can be only modified by
software while it is in empty state, refer to
The filter values can be modified either deactivating the associated filter banks or by setting
the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO
assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when
the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
42.9.2
CAN control and status registers
Refer to
CAN master control register (CAN_MCR)
Address offset: 0x00
Reset value: 0x0001 0002
31
30
29
Res.
Res.
Res.
15
14
13
RESET
Res.
Res.
rs
1470/1693
Reception of a new message, FMP1 bits in the CAN_RF1R register are not '00'.
FIFO1 full condition, FULL1 bit in the CAN_RF1R register set.
FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.
Error condition, for more details on error conditions please refer to the CAN Error
Status register (CAN_ESR).
Wakeup condition, SOF monitored on the CAN Rx signal.
Entry into Sleep mode.
Section 1.1
for a list of abbreviations used in register descriptions.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
Figure 483: Transmit mailbox
24
23
22
Res.
Res.
Res.
8
7
6
Res.
TTCM
ABOM
rw
rw
DocID024597 Rev 3
states.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
AWUM
NART
RFLM
TXFP
rw
rw
rw
rw
RM0351
17
16
Res.
DBF
rw
2
1
0
SLEEP
INRQ
rw
rw

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