Swpmi Interrupt Enable Register (Smpmi_Ier) - ST STM32L4x6 Reference Manual

RM0351
40.6.5

SWPMI Interrupt Enable register (SMPMI_IER)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:9 Reserved, must be kept at reset value
Bit 8 SRIE: Slave resume interrupt enable
Bit 7 TCIE: Transmit complete interrupt enable
Bit 6 TIE: Transmit interrupt enable
Bit 5 RIE: Receive interrupt enable
Bit 4 TXUNRIE: Transmit underrun error interrupt enable
Bit 3 RXOVRIE: Receive overrun error interrupt enable
Bit 2 RXBERIE: Receive CRC error interrupt enable
Bit 1 TXBEIE: Transmit buffer empty interrupt enable
Bit 0 RXBFIE: Receive buffer full interrupt enable
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever SRF flag is set in the SWPMI_ISR register
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever TCF flag is set in the SWPMI_ISR register
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever TXE flag is set in the SWPMI_ISR register
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever RXNE flag is set in the SWPMI_ISR register
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever TXBUNRF flag is set in the SWPMI_ISR
register
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever RXBOVRF flag is set in the SWPMI_ISR
register
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever RXBERF flag is set in the SWPMI_ISR
register
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever TXBEF flag is set in the SWPMI_ISR register
0: Interrupt is inhibited
1: An SWPMI interrupt is generated whenever RXBFF flag is set in the SWPMI_ISR register
Single Wire Protocol Master Interface (SWPMI)
24 23 22
Res. Res. Res.
8 7 6
SRIE TCIE TIE
rw rw rw
DocID024597 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
TXUNR RXOVR RXBEI
RIE
EIE EIE E
rw rw rw rw
17 16
Res. Res.
1 0
TXBERI
RXBFIE
E
rw rw
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