Table of Contents
Advertisement
RM0351
The behavior is to stop SDMMC_CK and freeze SDMMC state machines. The data transfer
is stalled while the FIFO is unable to transmit or receive data. Only state machines clocked
by SDMMCCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or
emptied even if flow control is activated.
To enable HW flow control, the SDMMC_CLKCR[14] register bit must be set to 1. After reset
Flow Control is disabled.
41.8
SDMMC registers
The device communicates to the system via 32-bit-wide control registers accessible via
APB2.
41.8.1
SDMMC power control register (SDMMC_POWER)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
[1:0] PWRCTRL: Power supply control bits.
These bits are used to define the current functional state of the card clock:
00: Power-off: the clock to card is stopped.
01: Reserved
10: Reserved power-up
11: Power-on: the card is clocked.
Note:
At least seven PCLK2 clock periods are needed between two write accesses to this register.
Note:
After a data write, data cannot be written to this register for three SDMMCCLK clock periods
plus two PCLK2 clock periods.
41.8.2
SDMMC clock control register (SDMMC_CLKCR)
Address offset: 0x04
Reset value: 0x0000 0000
The SDMMC_CLKCR register controls the SDMMC_CK output clock.
31
30
29
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
DocID024597 Rev 3
SD/SDIO/MMC card host interface (SDMMC)
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
21
Res.
Res.
Res.
Res.
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
PWRCTRL
rw
20
19
18
17
Res.
Res.
Res.
Res.
1435/1693
16
Res.
0
rw
16
Res.
1450
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32L4x6 and is the answer not in the manual?
Questions and answers