Baud Rate Register (Lpuart_Brr) - ST STM32L4x6 Reference Manual

RM0351
Bit 3 HDSEL: Half-duplex selection
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 EIE: Error interrupt enable
37.7.4

Baud rate register (LPUART_BRR)

This register can only be written when the LPUART is disabled (UE=0).
Address offset: 0x0C
Reset value: 0x0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 BRR[19:0]
Note: It is forbidden to write values less than 0x300 in the LPUART_BRR register.
Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, a care
should be taken when generating high baudrates using high fck values. fck must be in the
range [3 x baudrate,.4096 x baudrate].
37.7.5 Request register (LPUART_RQR)
Address offset: 0x18
Reset value: 0x0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Low-power universal asynchronous receiver transmitter (LPUART)
Selection of Single-wire Half-duplex mode
0: Half duplex mode is not selected
1: Half duplex mode is selected
This bit can only be written when the LPUART is disabled (UE=0).
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUART_ISR register).
0: Interrupt is inhibited
1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUART_ISR register.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
DocID024597 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
BRR[15:0]
rw rw rw rw
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
20 19 18 17
Res. BRR[19:16]
rw rw rw
4 3 2 1
rw rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. RXFRQ MMRQ SBKRQ
w w w
16
rw
0
rw
16
Res.
0
Res.
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