Otg Power Down Register (Otg_Gpwrdn) - ST STM32L4x6 Reference Manual

USB on-the-go full-speed (OTG_FS)

43.15.15 OTG power down register (OTG_GPWRDN)

Address offset: 0x058
Reset value: 0x0000 0010
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 ADPIF: ADP interrupt flag
Bits 22:1 Reserved, must be kept at reset value.
Bit 0 ADPMEN: ADP module enable
43.15.16 OTG ADP timer, control and status register
(OTG_GADPCTL)
Address offset: 0x060
Reset value: 0x0000 0000
The OTG_GADPCTL register must be accessed as follows:
•
In order to read from the OTG_GADPCTL register, program AR=0b01 and keep polling
till AR=0b00. The core updates the other fields of this register and makes AR=0b00.
Read values of this register are valid only when AR=0b00.
•
In order to write to the OTG_GADPCTL register, program AR=0b10 along with the
values for the other fields and keep polling till AR=0b00. When AR becomes 0b00, it
means that the programmed value has taken effect inside the core.
31 30 29
Res. Res. Res.
15 14 13
r r r
1548/1693
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set whenever there is an ADP event
This bit enables or disables the ADP logic.
0: Disable ADP module
1: Enable ADP module
28 27 26 25
ADP ADP
AR
TOIM SNSIM
rw rw rw rw
12 11 10 9
RTIM
r r r r
DocID024597 Rev 3
24 23 22 21
Res. ADPIF Res. Res.
rc_w1
8 7 6
Res. Res. Res. Res.
24 23 22 21
ADP ADP ADP ADP
PRBIM TOIF SNSIF PRBIF
rw rc_w1 rc_w1 rc_w1
8 7 6
r r r rw
20 19 18
Res. Res. Res.
5 4 3 2
Res. Res. Res.
20 19 18
ADP ENA
ADPEN
RST SNS
rw rs rw
5 4 3 2
PRBPER PRBDELTA
rw rw rw
RM0351
17 16
Res. Res.
1 0
ADPM
Res.
EN
rw
17 16
ENA
RTIM
PRB
rw r
1 0
PRBDSCHG
rw rw