RM0351
Caution:
In order to be I
below:
Symbol
SCL clock frequency
f
SCL
Hold time (repeated) START
t
HD:STA
condition
Set-up time for a repeated
t
SU:STA
START condition
Set-up time for STOP condition
t
SU:STO
Figure 365. Master clock generation
2
C or SMBus compliant, the master clock must respect the timings given
2
Table 179. I
C-SMBUS specification clock timings
Parameter
DocID024597 Rev 3
Inter-integrated circuit (I2C) interface
Standard-
Fast-mode
mode (Sm)
(Fm)
Min
Max
Min
Max
100
400
4.0
-
0.6
4.7
-
0.6
4.0
-
0.6
Fast-mode
SMBUS
Plus (Fm+)
Min
Max
Min
Max
1000
100
0.26
-
4.0
-
0.26
-
4.7
-
0.26
-
4.0
-
Unit
kHz
µs
µs
µs
1129/1693
1177
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