Lpuart Registers - ST STM32L4x6 Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
37.7

LPUART registers

Refer to
37.7.1 Control register 1 (LPUART_CR1)
Address offset: 0x00
Reset value: 0x0000
31 30 29
Res. Res. Res.
15 14 13
Res. CMIE MME
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Bits 31:29 Reserved, must be kept at reset value
Bit 28 M1: Word length
This bit, with bit 12 (M0) determines the word length. It is set or cleared by software.
M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits
This bit can only be written when the LPUART is disabled (UE=0).
Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Autobaudrate
Bit 27 Reserved, must be kept at reset value
Bit 26 Reserved, must be kept at reset value
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in UCLK (USART clock) clock cycles. For more
details, refer to RS485 Driver Enable paragraph.
This bit field can only be written when the LPUART is disabled (UE=0).
Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal. It is expressed in UCLK
(USART clock) clock cycles. For more details, refer to RS485 Driver Enable paragraph.
If the LPUART_TDR register is written during the DEDT time, the new data is transmitted
only when the DEDT and DEAT times have both elapsed.
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 15 Reserved, must be kept at reset value
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register.
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Section 1.1 on page 61
28 27 26 25
M1 Res. Res.
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12 11 10 9
M0 WAKE PCE PS
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(0x7F and 0x55 frames detection) are not supported.
for a list of abbreviations used in register descriptions.
24 23 22
DEAT[4:0]
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8 7 6
PEIE TXEIE TCIE
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DocID024597 Rev 3
21 20 19
DEDT[4:0]
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5 4 3
RXNEIE IDLEIE TE
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RM0351
18 17 16
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2 1 0
RE UESM UE
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