Debug Mcu Configuration Register (Dbgmcu_Cr) - ST STM32L4x6 Reference Manual

RM0351
44.16.2 Debug support for timers, RTC, watchdog, bxCAN and I
During a breakpoint, it is necessary to choose how the counter of timers,RTC and watchdog
should behave:
•
They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
• They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the bxCAN, the user can choose to block the update of the receive register during a
breakpoint.
2
For the I
The DBGMCU freeze registers can be written by the debugger under system reset. If the
debugger host does not support these features, it is still possible to write these registers by
software.
44.16.3

Debug MCU configuration register (DBGMCU_CR)

Address: 0xE004 2004
Power-on reset: 0x0000 0000
System reset: not affected
Access: Only 32-bit access supported
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control
– With TRACE_IOEN=0:
– With TRACE_IOEN=1:
Bits 4:3 Reserved, must be kept at reset value.
C, the user can choose to block the SMBUS timeout during a breakpoint.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
TRACE_MODE=xx: TRACE pins not assigned (default state)
– TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode
– TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 1
– TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 2
– TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 4
24 23 22
Res. Res. Res. Res.
8 7 6
TRACE_ TRACE
Res. MODE
[1:0] IOEN
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Debug support (DBG)
2
C
21 20 19 18
Res. Res. Res.
5 4 3 2
DBG_
_ Res.. Res. STAND
BY
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17 16
Res. Res.
1 0
DBG_ DBG_
STOP SLEEP
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