Status Register (Sai_Asr / Sai_Bsr) - ST STM32L4x6 Reference Manual

Serial audio interface (SAI)
39.5.7

Status register (SAI_ASR / SAI_BSR)

Address offset: block A: 0x018
Address offset: block B: 0x038
Reset value: 0x0000 0008
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:19 Reserved, always read as 0.
Bits 18:16 FLTH: FIFO level threshold.
This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting
depends on SAI block configuration (transmitter or receiver mode).
If the SAI block is configured as transmitter:
000: FIFO empty
001: FIFO <= ¼ but not empty
010: ¼ < FIFO <= ½
011: ½ < FIFO <= ¾
100: ¾ < FIFO but not full
101: FIFO full
If SAI block is configured as receiver:
000: FIFO empty
001: FIFO < ¼ but not empty
010: ¼ <= FIFO < ½
011: ½ =< FIFO < ¾
100: ¾ =< FIFO but not full
101: FIFO full
Bits 15:7 Reserved, always read as 0.
Bit 6 LFSDET: Late frame synchronization detection.
This bit is read only.
0: No error.
1: Frame synchronization signal is not present at the right time.
This flag can be set only if the audio block is configured in slave mode.
It is not used in AC'97 or SPDIF mode.
It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register.
This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register
Bit 5 AFSDET: Anticipated frame synchronization detection.
This bit is read only.
0: No error.
1: Frame synchronization signal is detected earlier than expected.
This flag can be set only if the audio block is configured in slave mode.
It is not used in AC'97 or SPDIF mode.
It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register.
This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.
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27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
DocID024597 Rev 3
23 22 21 20
Res. Res. Res. Res.
7 6 5
Res. LFSDET AFSDET CNRDY
r r
19 18
Res.
r
4 3 2
FREQ WCKCFG MUTEDET OVRUDR
r r r
RM0351
17 16
FLTH
r r
1 0
r r