Otg Device All Endpoints Interrupt Register (Otg_Daint) - ST STM32L4x6 Reference Manual

USB on-the-go full-speed (OTG_FS)
43.15.36 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK)
Address offset: 0x814
Reset value: 0x0000 0000
This register works with each of the OTG_DOEPINTx registers for all endpoints to generate
an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the
OTG_DOEPINTx register can be masked by writing into the corresponding bit in this
register. Status bits are masked by default.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:5 Reserved, must be kept at reset value for USB OTG FS.
Bit 6 Reserved, must be kept at reset value for USB OTG FS.
Bit 4 OTEPDM: OUT token received when endpoint disabled mask. Applies to control OUT
endpoints only.
Bit 3 STUPM: STUPM: SETUP phase done mask. Applies to control endpoints only.
Bit 2 Reserved, must be kept at reset value.
Bit 1 EPDM: Endpoint disabled interrupt mask
Bit 0 XFRCM: Transfer completed interrupt mask

43.15.37 OTG device all endpoints interrupt register (OTG_DAINT)

Address offset: 0x818
Reset value: 0x0000 0000
When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the
application using the Device OUT endpoints interrupt bit or Device IN endpoints interrupt bit
of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There
is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits
for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits
1568/1693
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
DocID024597 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. OTEPD STUPM Res.
M
rw rw
RM0351
17 16
Res. Res.
1 0
XFRC
EPDM
M
rw rw