Table of Contents
Advertisement
RM0351
40.6.2
SWPMI Bitrate register (SWPMI_BRR)
Address offset: 0x04
Reset value: 0x0000 0001
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:6 Reserved, must be kept at reset value
Bits 5:0 BR[5:0]: Bitrate prescaler
This field must be programmed to set SWP bus bitrate, taking into account the F
programmed in the RCC (Reset and Clock Control), according to the following formula:
F
SWP
Note: The programmed bitrate must stay within the following range: from 100 kbit/s up to
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
= F
/ ((BR[5:0]+1)x4)
SWPCLK
2 Mbit/s.
BR[5:0] cannot be written while SWPACT bit is set in the SWPMI_CR register.
DocID024597 Rev 3
Single Wire Protocol Master Interface (SWPMI)
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
rw
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
BR[5:0]
rw
rw
rw
rw
SWPCLK
16
Res.
0
rw
1383/1685
1392
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32L4x6 and is the answer not in the manual?
Questions and answers