Sdmmc Data Fifo Register (Sdmmc_Fifo) - ST STM32L4x6 Reference Manual

SD/SDIO/MMC card host interface (SDMMC)
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 FIFOCOUNT: Remaining number of words to be written to or read from the FIFO.
41.8.15

SDMMC data FIFO register (SDMMC_FIFO)

Address offset: 0x80
Reset value: 0x0000 0000
The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs
contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store
multiple operands to read from/write to the FIFO.
31 30 29
rw rw rw
15 14 13
rw rw rw
bits 31:0 FIFOData: Receive and transmit FIFO data
1448/1693
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
The FIFO data occupies 32 entries of 32-bit words, from address:
SDMMC base + 0x080 to SDMMC base + 0xFC.
DocID024597 Rev 3
24 23 22
Res.
r r
8 7 6
FIFOCOUNT[15:0]
r r r
24 23 22
FIF0Data[31:16]
rw rw rw
8 7 6
FIF0Data[15:0]
rw rw rw
21 20 19 18
FIFOCOUNT[23:16]
r r r r
5 4 3 2
r r r r
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0351
17 16
r r
1 0
r r
17 16
rw rw
1 0
rw rw