Sdmmc Data Length Register (Sdmmc_Dlen) - ST STM32L4x6 Reference Manual

SD/SDIO/MMC card host interface (SDMMC)
41.8.8

SDMMC data length register (SDMMC_DLEN)

Address offset: 0x28
Reset value: 0x0000 0000
The SDMMC_DLEN register contains the number of data bytes to be transferred. The value
is loaded into the data counter when data transfer starts.
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bits 24:0 DATALENGTH: Data length value
Number of data bytes to be transferred.
Note: For a block data transfer, the value in the data length register must be a multiple of the block
size (see SDMMC_DCTRL). A data transfer must be written to the data timer register and
the data length register before being written to the data control register.
For an SDMMC multibyte transfer the value in the data length register must be between 1
and 512.
41.8.9 SDMMC data control register (SDMMC_DCTRL)
Address offset: 0x2C
Reset value: 0x0000 0000
The SDMMC_DCTRL register control the data path state machine (DPSM).
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 SDIOEN: SD I/O enable functions
If this bit is set, the DPSM performs an SD I/O-card-specific operation.
Bit 10 RWMOD: Read wait mode
0: Read Wait control stopping SDMMC_D2
1: Read Wait control using SDMMC_CK
1440/1693
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
SDIO RW RW
EN MOD STOP
rw rw rw
DocID024597 Rev 3
24 23 22
rw rw rw
8 7 6
DATALENGTH[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
RW
DBLOCKSIZE
START
rw rw rw
21 20 19 18
DATALENGTH[24:16]
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
DMA DT
EN MODE
rw rw rw rw
RM0351
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
DTDIR DTEN
rw rw