Table 244. R2 Response; R2 (Cid, Csd Register) - ST STM32L4x6 Reference Manual

SD/SDIO/MMC card host interface (SDMMC)
41.5.2 R1b
It is identical to R1 with an optional busy signal transmitted on the data line. The card may
become busy after receiving these commands based on its state prior to the command
reception.
41.5.3

R2 (CID, CSD register)

Code length = 136 bits. The contents of the CID register are sent as a response to the
CMD2 and CMD10 commands. The contents of the CSD register are sent as a response to
CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of
these registers is replaced by the end bit of the response. The card indicates that an erase
is in progress by holding SDMMC_D0 low. The actual erase time may be quite long, and the
host may issue CMD7 to deselect the card.
Bit position
135
134
[133:128]
[127:1]
0
1430/1693

Table 244. R2 response

Width (bits
1 0
1 0
6 '111111'
127 X
1 1
DocID024597 Rev 3
Value
Start bit
Transmission bit
Command index
Card status
End bit
RM0351
Description