Figure 428. Data Alignment When Data Length Is Not Equal To 8-Bit Or 16-Bit; Configuration Of Spi - ST STM32L4x6 Reference Manual

Serial peripheral interface (SPI)

Figure 428. Data alignment when data length is not equal to 8-bit or 16-bit

Note: The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced
to an 8-bit data frame size.
38.4.7

Configuration of SPI

The configuration procedure is almost the same for master and slave. For specific mode
setups, follow the dedicated sections. When a standard communication is to be initialized,
perform these steps:
1. Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
2. Write to the SPI_CR1 register:
a)
b)
c)
d)
e)
f)
g)
3. Write to SPI_CR2 register:
a)
b)
c)
d)
e)
f)
4. Write to SPI_CRCPR register: Configure the CRC polynomial if needed.
5. Write proper DMA registers: Configure DMA streams dedicated for SPI Tx and Rx in
DMA registers if the DMA streams are used.
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Configure the serial clock baud rate using the BR[2:0] bits
Configure the CPOL and CPHA bits combination to define one of the four
relationships between the data transfer and the serial clock (CPHA must be
cleared in NSSP mode).
Select simplex or half-duplex mode by configuring RXONLY or BIDIMODE and
BIDIOE (RXONLY and BIDIMODE can't be set at the same time).
Configure the LSBFIRST bit to define the frame format
Configure the CRCL and CRCEN bits if CRC is needed (while SCK clock signal is
at idle state).
Configure SSM and SSI
Configure the MSTR bit (in multimaster NSS configuration, avoid conflict state on
NSS if master is configured to prevent MODF error).
Configure the DS[3:0] bits to select the data length for the transfer.
Configure SSOE (Note:
Set the FRF bit if the TI protocol is required (keep NSSP bit cleared in TI mode).
Set the NSSP bit if the NSS pulse mode between two data units is required (keep
CHPA and TI bits cleared in NSSP mode).
Configure the FRXTH bit. The RXFIFO threshold must be aligned to the read
access size for the SPIx_DR register.
Initialize LDMA_TX and LDMA_RX bits if DMA is used in packed mode.
DocID024597 Rev 3
(Note: 2).
(Note: 2 & 3).
1 & 2 & 3).
RM0351
(Note: 4).
(Note: 2).