Figure 418. Rs232 Cts Flow Control - ST STM32L4x6 Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
transmission does not occur. When CTS is de-asserted during a transmission, the current
transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the LPUART_CR3 register is set.
shows an example of communication with CTS flow control enabled.
Note: For correct behavior, CTS must be asserted at least 3 LPUART clock source periods before
the end of the current character. In addition it should be noted that the CTSCF flag may not
be set for pulses shorter than 2 x PCLK periods.
RS485 Driver Enable
The driver enable feature is enabled by setting bit DEM in the LPUART_CR3 control
register. This allows the user to activate the external transceiver control, through the DE
(Driver Enable) signal. The assertion time is the time between the activation of the DE signal
and the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the
LPUART_CR1 control register. The de-assertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bit fields in the LPUART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the LPUART_CR3 control register.
In LPUART, the DEAT and DEDT are expressed in USART clock source (f
•
The Driver enable assertion time =
–
–
•
The Driver enable de-assertion time =
–
–
With P = BRR[14:11]
1264/1693

Figure 418. RS232 CTS flow control

(1 + (DEAT x P)) x f
CK
(1 + DEAT) x f , if P = 0
CK
(1 + (DEDT x P)) x f
CK
(1 + DEDT) x f , if P = 0
CK
DocID024597 Rev 3
, if P <> 0
, if P <> 0
RM0351
Figure 406
) cycles:
CK