I2C Master Mode - ST STM32L4x6 Reference Manual

Inter-integrated circuit (I2C) interface
35.4.8

I2C master mode

I2C master initialization
Before enabling the peripheral, the I2C master clock must be configured by setting the
SCLH and SCLL bits in the I2C_TIMINGR register.
A clock synchronization mechanism is implemented in order to support multi-master
environment and slave clock stretching.
In order to allow clock synchronization:
•
The low level of the clock is counted using the SCLL counter, starting from the SCL low
level internal detection.
•
The high level of the clock is counted using the SCLH counter, starting from the SCL
high level internal detection.
The I2C detects its own SCL low level after a
edge, SCL input noise filters (analog + digital) and SCL synchronization to the I2CxCLK
clock. The I2C releases SCL to high level once the SCLL counter reaches the value
programmed in the SCLL[7:0] bits in the I2C_TIMINGR register.
The I2C detects its own SCL high level after a
edge, SCL input noise filters (analog + digital) and SCL synchronization to I2CxCLK clock.
The I2C ties SCL to low level once the SCLH counter is reached reaches the value
programmed in the SCLH[7:0] bits in the I2C_TIMINGR register.
Consequently the master clock period is:
t t
SCL = SYNC1
The duration of t
–
–
–
–
The duration of t
–
–
–
–
1128/1693
+ t {[(SCLH+1) + (SCLL+1)] x (PRESC+1) x t
SYNC2 +
depends on these parameters:
SYNC1
SCL falling slope
When enabled, input delay induced by the analog filter.
When enabled, input delay induced by the digital filter: DNF
Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)
depends on these parameters:
SYNC2
SCL rising slope
When enabled, input delay induced by the analog filter.
When enabled, input delay induced by the digital filter: DNF
Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)
DocID024597 Rev 3
delay depending on the SCL falling
t
SYNC1
delay depending on the SCL rising
t
SYNC2
I2CCLK
RM0351
}
x t
I2CCLK
x t
I2CCLK