Usart Irda Sir Endec Block - ST STM32L4x6 Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
The software checks the received character against these two patterns and, if any of them
match, then programs the USART accordingly for the next character reception.
If none of the two is recognized, a card reset may be generated in order to restart the
negotiation.
36.5.14

USART IrDA SIR ENDEC block

This section is relevant only when IrDA mode is supported. Please refer to
USART implementation on page
IrDA mode is selected by setting the IREN bit in the USARTx_CR3 register. In IrDA mode,
the following bits must be kept cleared:
•
LINEN, STOP and CLKEN bits in the USARTx_CR2 register,
•
SCEN and HDSEL bits in the USARTx_CR3 register.
The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation
scheme that represents logic 0 as an infrared light pulse (see
The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream
output from USART. The output pulse stream is transmitted to an external output driver and
infrared LED. USART supports only bit rates up to 115.2 Kbps for the SIR ENDEC. In
normal mode the transmitted pulse width is specified as 3/16 of a bit period.
The SIR receive decoder demodulates the return-to-zero bit stream from the infrared
detector and outputs the received NRZ serial bit stream to the USART. The decoder input is
normally high (marking state) in the Idle state. The transmit encoder output has the opposite
polarity to the decoder input. A start bit is detected when the decoder input is low.
•
IrDA is a half duplex communication protocol. If the Transmitter is busy (when the
USART is sending data to the IrDA encoder), any data on the IrDA receive line is
ignored by the IrDA decoder and if the Receiver is busy (when the USART is receiving
decoded data from the IrDA decoder), data on the TX from the USART to IrDA is not
encoded. while receiving data, transmission should be avoided as the data to be
transmitted could be corrupted.
•
A 0 is transmitted as a high pulse and a 1 is transmitted as a 0. The width of the pulse
is specified as 3/16th of the selected bit period in normal mode (see
• The SIR decoder converts the IrDA compliant receive signal into a bit stream for
USART.
•
The SIR receive logic interprets a high state as a logic one and low pulses as logic
zeros.
•
The transmit encoder output has the opposite polarity to the decoder input. The SIR
output is in low state when Idle.
• The IrDA specification requires the acceptance of pulses greater than 1.41 µs. The
acceptable pulse width is programmable. Glitch detection logic on the receiver end
filters out pulses of width less than 2 PSC periods (PSC is the prescaler value
programmed in the USARTx_GTPR). Pulses of width less than 1 PSC period are
always rejected, but those of width greater than one and less than two periods may be
accepted or rejected, those greater than 2 periods will be accepted as a pulse. The
IrDA encoder/decoder doesn't work when PSC=0.
•
The receiver can communicate with a low-power transmitter.
• In IrDA mode, the STOP bits in the USARTx_CR2 register must be configured to "1
stop bit".
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DocID024597 Rev 3
RM0351
Section 36.4:
Figure 400).
Figure 401).