Figure 359. Transfer Sequence Flowchart For I2C Slave Transmitter, Nostretch=0 - ST STM32L4x6 Reference Manual

RM0351
the number of TXIS events during the transfer corresponds to the value programmed in
NBYTES.
Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so the
user cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to
program the first data byte. The first data byte to be sent must be previously programmed in
the I2C_TXDR register:
•
This data can be the data written in the last TXIS event of the previous transmission
message.
•
If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by
setting the TXE bit in order to program a new data byte. The STOPF bit must be
cleared only after these actions, in order to guarantee that they are executed before the
first data transmission starts, following the address acknowledge.
If STOPF is still set when the first data transmission starts, an underrun error will be
generated (the OVR flag is set).
If a TXIS event is needed, (Transmit Interrupt or Transmit DMA request), the user must
set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event.

Figure 359. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0

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