Table 249. R6 Response; Sdio I/O Card-Specific Operations - ST STM32L4x6 Reference Manual

RM0351
47
46
[45:40]
[39:8] Argument
field
[7:1]
0
The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case,
the 16 bits of response are the SD I/O-only values:
•
Bit [15] COM_CRC_ERROR
•
Bit [14] ILLEGAL_COMMAND
•
Bit [13] ERROR
•
Bits [12:0] Reserved
41.6

SDIO I/O card-specific operations

The following features are SD I/O-specific operations:
•
SDIO read wait operation by SDMMC_D2 signalling
•
SDIO read wait operation by stopping the clock
•
SDIO suspend/resume operation (write and read suspend)
•
SDIO interrupts
The SDMMC supports these operations only if the SDMMC_DCTRL[11] bit is set, except for
read suspend that does not need specific hardware implementation.
41.6.1 SDIO I/O read wait operation by SDMMC_D2 signalling
It is possible to start the readwait interval before the first block is received: when the data
path is enabled (SDMMC_DCTRL[0] bit set), the SDIO-specific operation is enabled
(SDMMC_DCTRL[11] bit set), read wait starts (SDMMC_DCTRL[10] =0 and
SDMMC_DCTRL[8] =1) and data direction is from card to SDMMC (SDMMC_DCTRL[1] =
1), the DPSM directly moves from Idle to Readwait. In Readwait the DPSM drives
SDMMC_D2 to 0 after 2 SDMMC_CK clock cycles. In this state, when you set the RWSTOP
bit (SDMMC_DCTRL[9]), the DPSM remains in Wait for two more SDMMC_CK clock cycles
to drive SDMMC_D2 to 1 for one clock cycle (in accordance with SDIO specification). The
DPSM then starts waiting again until it receives data from the card. The DPSM will not start
a readwait interval while receiving a block even if read wait start is set: the readwait interval
will start after the CRC is received. The RWSTOP bit has to be cleared to start a new read
wait operation. During the readwait interval, the SDMMC can detect SDIO interrupts on
SDMMC_D1.
Bit position Width (bits)
1
1
6
[31:16] 16
[15:0] 16
7
1
SD/SDIO/MMC card host interface (SDMMC)

Table 249. R6 response

Value
0
0
'101000'
X
X
X
1
DocID024597 Rev 3
Description
Start bit
Transmission bit
CMD40
RCA [31:16] of winning card or of the host
Not defined. May be used for IRQ data
CRC7
End bit
1433/1693
1450