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T RDYA
When used for this function, this signal reflects the complement of the status of bit 2 of
the channel A status register. This signal can be used to control parallel data flow by
acting as an interrupt to indicate when the transmitter contains a character.
OP6
When used for this function, this output is controlled by bit 6 in the output port data
registers.
2.13.8 Receiver Ready (R RDYA)
This active-low output signal can be programmed as the channel A receiver ready,
channel A FIFO full indicator, or a dedicated parallel output.
R RDYA
When used for this function, this signal reflects the complement of the status of bit 1 of
the interrupt status register. This signal can be used to control parallel data flow by
acting as an interrupt to indicate when the receiver contains a character.
FFULLA
When used for this function, this signal reflects the complement of the status of bit 1 of
the interrupt status register. This signal can be used to control parallel data flow by
acting as an interrupt to indicate when the receiver FIFO is full.
OP4
When used for this function, this output is controlled by bit 4 in the output port data
registers.
2.14 TIMER SIGNALS
The following external signals are used by the timer modules. See Section 8 Timer
Modules for additional information on these signals.
2.14.1 Timer Gate ( TGATE2, TGATE1 )
These active-low inputs can be programmed to enable and disable the counters and
prescalers. TGATE can also be programmed as a simple input.
2.14.2 Timer Input (TIN2, TIN1)
These inputs can be programmed as clocks that cause events to occur in the counters
and prescalers.
2.14.3 Timer Output (TOUT2, TOUT1)
These outputs drive the various output waveforms generated by the timers.
2-12
Freescale Semiconductor, Inc.
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
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