Dma Controller Overview; Basic Operation - Motorola DragonBall MC68328 User Manual

4.6 DMA CONTROLLER OVERVIEW

The LCD DMA controller is a flyby type, 16-bit wide, fast-data transfer machine. Because
the LCD screen has to be refreshed continuously at a rate of about 50-70 Hz, in this case,
the pixel bits in the memory will be read and transferred to corresponding pixels on the
screen. To minimize the bus obstruction because of bus-sharing with the system, a burst
type and flyby transfer is therefore required. The refresh is divided into small packs of 8- or
16-word reads. Every time the internal line buffer needs data, it will assert the BR signal to
request the bus from the MC68EC000. Once the MC68EC000 core grants the bus (i.e. BG
is asserted), the DMA controller will get control of the bus signal and issue 8- or 16-word
reads (see setting of CKCON register) from memory. The read data is then passed to the
next stage internally to generate the LCD timing (flyby). During the LCD access cycles, out-
put- enable and chip-select signals for the corresponding system SRAM chip will be
asserted by the chip-select logic inside the SIM. The minimum bus bandwidth obstruct can
be achieved by using zero LCD-access wait states (1 clock per access). See Section 4-8
Bandwidth Calculation and Saving for more details.

4.6.1 Basic Operation

As shown in Figure 4-6 and Figure 4-7, data is fetched from memory in a very efficient man-
ner. Each burst is limited to 8/16 words, which reduces possible latency for other peripherals
such as the interrupt controller. For example, the average time latency for LCDCLK = 5MHz
with 16-word burst is approximately 2.4 s.
SYSCLK
BR
BG
ADDRESS
DATA
OE
CS
Figure 4-6. Three Clock per LCD DMA Transfer (2 Wait States)
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
LCD Controller
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