Motorola PowerQUICC II MPC8280 Series Reference Manual page 317

8.5.4 Effect of ARTRY Assertion on Data Transfer and
Arbitration
The MPC8280 allows an address tenure to overlap its associated data tenure. The
MPC8280 internally guarantees that the first TA of the data tenure is delayed to be at the
same time or after the ARTRY window (the clock after the assertion of AACK).
8.5.5 Port Size Data Bus Transfers and PSDVAL Termination
The MPC8280 can transfer data via data ports of 8, 16, 32, and 64 bits, as shown in
Section 8.4.3, "Address Transfer Attribute Signals." Single-beat transaction sizes can be 8,
16, 32, 64, 128, and 192 bits; burst transactions are 256 bits. Single-beat and burst
transactions are divided into to a number of intermediate beats depending on the port size.
The MPC8280 asserts PSDVAL to mark the cycle in which data is accepted. Assertion of
PSDVAL in conjunction with TA marks the end of the transfer in single-beat mode. The
fourth assertion of PSDVAL in conjunction with TA signals the end of a burst transfer.
Figure 8-9 shows an extended transaction of 4 words to a port size of 32 bits. The
single-beat transaction is translated to four port-sized beats.
CLKOUT
ADDR + ATTR
TS
AACK
DBG
PSDVAL
TA
D[0–31]
Figure 8-9. 28-Bit Extended Transfer to 32-Bit Port Size
MOTOROLA
Freescale Semiconductor, Inc.
D0 D1 D2
Chapter 8. The 60x Bus
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Data Tenure Operations
D3
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