Texas Instruments MSPM0G310 Series Manual
Texas Instruments MSPM0G310 Series Manual

Texas Instruments MSPM0G310 Series Manual

Mixed-signal microcontrollers with can-fd interface
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MSPM0G310x Mixed-Signal Microcontrollers with CAN-FD Interface

1 Features

Core
– Arm
®
32-bit Cortex
®
protection unit, frequency up to 80 MHz
Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62 V to 3.6 V
Memories
– Up to 128KB of flash memory with built-in error
correction code (ECC)
– Up to 32KB of ECC protected SRAM with
hardware parity
High-performance analog peripherals
– Two simultaneous sampling 12-bit 4-Msps
analog-to-digital converters (ADC's) with up to
11 external channels
14-bit effective resolution at 250-ksps with
hardware averaging
– One general-purpose amplifier (GPAMP)
– Configurable 1.4-V or 2.5-V internal shared
voltage reference (VREF)
– Integrated temperature sensor
Optimized low-power modes
– RUN: 96 µA/MHz (CoreMark)
– SLEEP: 458 µA at 4 MHz
– STOP: 47 µA at 32 kHz
– STANDBY: 1.5 µA with RTC and SRAM
retention
– SHUTDOWN: 78 nA with IO wakeup capability
Intelligent digital peripherals
– 7-channel DMA controller
– Two 16-bit advanced control timers supporting
dead band insertion and fault handling
– Seven timers supporting up to 22 PWM
channels
One 16-bit general purpose timer
One 16-bit general purpose timer supports
QEI
Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
One 32-bit general-purpose timer
Two 16-bit advanced timers with deadband
– Two window-watchdog timers
– RTC with alarm and calendar mode
Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
-M0+ CPU with memory
MSPM0G3107, MSPM0G3106, MSPM0G3105
SLASF12A – FEBRUARY 2023 – REVISED JUNE 2023
2
– Two I
C interfaces supporting up to FM+
(1 Mbit/s), SMBus/PMBus, and wakeup from
STOP mode
– Two SPI interfaces, with one SPI interface
supporting upto 32Mbits/s
– One Controller Area Network (CAN) interface
supports CAN 2.0 A or B and CAN-FD
Clock system
– Internal 4- to 32-MHz oscillator with upto ±1.2%
accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80 MHz
– Internal 32-kHz oscillator (LFOSC)
– External 4- to 48-MHz crystal oscillator (HFXT)
– External 32-kHz crystal oscillator(LFXT)
– External clock input
Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
– True random number generator (TRNG)
– AES encryption with 128 or 256-bit key
Flexible I/O features
– Up to 28 GPIOs
Two 5-V tolerant IOs
Two high-drive IOs with 20-mA drive
strength
Development support
– 2-pin serial wire debug (SWD)
Package options
– 32-pin VQFN
– 28-pin VSSOP
– 20-pin VSSOP
Family members (also see
– MSPM0G3105: 32KB flash, 16KB RAM
– MSPM0G3106: 64KB flash, 32KB RAM
– MSPM0G3107: 128KB flash, 32KB RAM
Development kits and software (also see
and
Software)
LP-MSPM0G3507 LaunchPad
kit
– MSP Software Development Kit (SDK)

2 Applications

Motor control
Home appliances
Uninterruptible power supplies and inverters
Electronic point of sale systems
Medical and healthcare
Test and measurement
Factory automation and control
Industrial transport
Grid infrastructure
Smart metering
Device
Comparison)
Tools
development

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Summary of Contents for Texas Instruments MSPM0G310 Series

  • Page 1: Features

    MSPM0G3107, MSPM0G3106, MSPM0G3105 SLASF12A – FEBRUARY 2023 – REVISED JUNE 2023 MSPM0G310x Mixed-Signal Microcontrollers with CAN-FD Interface – Two I C interfaces supporting up to FM+ 1 Features (1 Mbit/s), SMBus/PMBus, and wakeup from • Core STOP mode – Two SPI interfaces, with one SPI interface –...
  • Page 2: Description

    See MSP430™ System-Level ESD Considerations for more information. The principles in this application note are applicable to MSPM0 MCUs. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 3: Functional Block Diagram

    PD1, CPU ACCESS ONLY HFXIN, HFXOUT VCORE, NRST PD1, CPU/DMA ACCESS ROSC PD1/PD0, CPU/DMA ACCESS CLK_OUT, FCC_IN PD0, CPU/DMA ACCESS Figure 4-1. MSPM0G310x Functional Block Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 4: Table Of Contents

    Caution......61 8.3 Power Management Unit (PMU)....... 10.8 Glossary..............61 8.4 Clock Module (CKM)..........41 11 Mechanical, Packaging, and Orderable 8.5 DMA................Information..............8.6 Events............... 12 Revision History............Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 5: Device Comparison

    The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section For more infromation about the device name, see Section 10.2. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 6: Pin Configuration And Functions

    PA15 / A1_0 PA3 / LFXIN PA14 / CLK_OUT / A0_12 PA13 PA4 / LFCLK_IN / LFXOUT Thermal pad Figure 6-2. 32-Pin RHB(VQFN) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 7 PA4 / LFCLK_IN / LFXOUT PA15 / A1_0 PA14 / CLK_OUT / A0_12 PA11 PA10 / CLK_OUT PA9 / RTC_OUT / CLK_OUT Figure 6-3. 28-Pin DGS28(VSSOP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 8 PA9 / RTC_OUT / CLK_OUT Figure 6-4. 20-Pin DGS20 (VSSOP) (Top View) Note For full pin configuration and functions for each package option, refer to Pin Attributes Signal Descriptions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 9: Pin Attributes

    TIMA1_C0 [8] UART3_RX [2] / UART2_RTS [3] / I2C1_SDA [4] / TIMA0_C3N[5] / UART1_RTS [6] / TIMG6_C1 [7] / – – – Standard TIMA1_C1 [8] Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 10 PA18 UART1_RX [2] / SPI1_PICO [3] / I2C1_SDA [4] / Standard with A1_3 / GPAMP_IN- TIMA0_C3N [5] / TIMG7_C1 [6] / TIMA1_C1 [7] wake Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 11 Table 6-2. Digital IO Features by IO Type DRIVE INVERSION HYSTERESIS PULLUP PULLDOWN WAKEUP IO STRUCTURE STRENGTH CONTROL CONTROL RESISTOR RESISTOR LOGIC CONTROL Standard drive Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 12: Signal Descriptions

    Default I C BSL data BSLRX Default UART BSL receive BSL (UART) BSLTX Default UART BSL transmit CAN_TX CAN-FD transmit data CAN_RX CAN-FD receive data Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 13 Serial wire debug data input/output FCC_IN Frequency clock counter input GPAMP_IN+ GPAMP non-inverting terminal input General- Purpose GPAMP_IN- GPAMP inverting terminal input Amplifier GPAMP_OUT GPAMP output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 14 – – – General-purpose digital I/O PA30 – – – General-purpose digital I/O PA31 – – – General-purpose digital I/O with wake up from SHUTDOWN Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 15 Power VCORE Regulated core power supply output QFN package exposed thermal pad. TI recommends QFN Pad – – connection to V RTC_OUT RTC clock output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 16 General purpose timer 7 CCR1 capture input/ compare output Timer TIMG7_C1 General purpose timer 7 CCR1 capture input/ compare output TIMG8_C0 General purpose timer 8 CCR0 capture input/ compare output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 17 TIMA1_C0N – output (inverting) Advanced control timer 1 CCR1 capture input/ compare TIMA1_C1 output Advanced control timer 1 CCR1 capture input/ compare TIMA1_C1N output (inverting) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 18 When using VREF+/- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 19: Connections For Unused Pins

    Section 9.1 Any unused pin with a function that is shared with general-purpose I/O should follow the "PAx and PBx" unused pin connection guidelines. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 20: Specifications

    MCLK, CPUCLK frequency with 2 flash wait states MCLK, CPUCLK frequency with 1 flash wait state MCLK (PD1 bus clock) MCLK, CPUCLK frequency with 0 flash wait states Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 21: Thermal Information

    Junction-to-case (bottom) thermal resistance °C/W θJC(bot) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 22: Supply Current Characteristics

    STANDBY Mode LFCLK=LFXT, STOPCLKSTBY=0, 6.91 STBY0 RTC enabled LFCLK=LFOSC, STOPCLKSTBY=1, 15.5 RTC enabled 32kHz LFCLK=LFXT, STOPCLKSTBY=1, 15.5 STBY1 RTC enabled LFCLK=LFXT, STOPCLKSTBY=1, 15.6 GPIOA enabled Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 23: Power Supply Sequencing

    Device operating in RUN, SLEEP, or STOP mode. 7.6.2 Power Supply Ramp Figure 7-1 gives the relationship of POR- POR+, BOR0-, and BOR0+ during power-up and power-down. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 24: Flash Memory Characteristics

    Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 25: Timing Characteristics

    The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 26: Clock Specifications

    , after which the target accuracy is SYSOSC settle,SYSOSC settle,SYSOSC achieved. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 27 The LFCLK monitor may be used to monitor the LFXT or LFCLK_IN. It will always fault below the MIN fault frequency, and will never fault above the MAX fault frequency. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 28: Digital Io

    All I/O except 0.1*VDD ODIO (2) (3) High-Z leakage current SDIO All I/O except Pull up resistance kΩ ODIO Pull down resistance kΩ Input capacitance Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 29 ≤130 °C VDD≥2.7V, DRV=1, |I =20mA ,max VDD-0.4 VDD≥1.71V, DRV=1, |I =10mA ,max HDIO VDD≥2.7V, DRV=0, |I =6mA ,max VDD-0.4 VDD≥1.71V, DRV=0, |I =2mA ,max Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 30 VDD ≥ 2.7V, DRV = 0, CL= 20pF ODIO VDD ≥ 1.71V, FM , CL= 20pF - 100pF All output ports Output rise/fall time VDD ≥ 1.71V 0.3*f except ODIO Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 31: Analog Mux Vboost

    R– All external reference specifications are measured with V = VREF+ = VDD = 3.3V and V = VREF- = VSS = 0V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 32 Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: 1. Tau = (R )* C 2. K= ln(2 /Settling error) – ln((C Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 33: Temperature Sensor

    A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable The VREF module should only be enabled when C is connected and should not be enabled otherwise. VREF Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 34: Gpamp

    GPAMP disable time disable Cycles = 200 pF, Vstep = 0.3V to VDD - GPAMP settling time Noninverting, unity gain µs SETTLE 0.3V, 0.1%, ENABLE = 0x1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 35: I2C

    (unless otherwise noted) PARAMETERS TEST CONDITIONS UNIT Clock max speed = 32MHz SPI clock frequency 1.62 < VDD < 3.6V Controller mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 36 Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 37: Uart

    UART BITCLK clock frequency(equals UART in Power Domain1 BITCLK baud rate in MBaud) BITCLK clock frequency(equals UART in Power Domain0 BITCLK baud rate in MBaud) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 38: Timx

    51.2 µs LAT256 20MHz 7.21 Emulation and Debug 7.21.1 SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT SWD frequency Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 39: Detailed Description

    OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 40 TIMA0, TIMA1 TIMG6, TIMG7 TIMG12 TIMG0, TIMG8 Peripherals UART0/1/2 I2C0/1 GPIOA/B WWDT0/1 Analog TRNG ADC0/1 NS (triggers supported) GPAMP IOMUX and IO Wakeup DIS w/ WAKE Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 41: Power Management Unit (Pmu)

    LFCLK: 32kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes • ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 42: Dma

    SPI0 Publisher 1 ADC1 Publisher 2 SPI0 Publisher 2 For more details, see the DMA chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 43: Events

    The following table summarizes the memory map of the devices. For more information about the memory region detail, see Platform Memory Map section in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 44 Table 8-5. Peripherals Summary Peripheral Name Base Address Size VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 WWDT1 0x40082000 0x2000 TIMG0 0x40084000 0x2000 TIMG8 0x40090000 0x2000 0x40094000 0x2000 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 45 0x40558000 0x1000 TIMA0 0x40860000 0x2000 TIMA1 0x40862000 0x2000 TIMG6 0x40868000 0x2000 TIMG7 0x4086A000 0x2000 TIMG12 0x40870000 0x2000 Aliased region of ADC0 and ADC1 memory-mapped registers Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 46: Flash Memory

    (devices with 32kB support 100,000 cycles on the entire flash memory) For a complete description of the flash memory, see the NVM chapter of the technical reference manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 47: Sram

    – MCU supply voltage (VDD) – External reference supplied to the ADC through the VREF+ and VREF- pins • Operates in RUN, SLEEP, and STOP modes Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 48: Temperature Sensor

    The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features: • Software selectable chopper stabilization Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 49: Trng

    Separated transmit and receive FIFOs support DAM data transfer • Support transmit and receive loopback mode operation • Table 8-8 for detail information on supported protocols Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 50: I2C

    MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Only SPI signals on HSIO pins support data rate > 16 Mbits/s; see the Pin Diagrams section for HSIO pins. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 51: Can-Fd

    The timer peripherals in these devices support the following key features, for specific configuration see Table 8-9: Specific features for the general-purpose timer (TIMGx) include: • 16-bit up, down, up-down or down-up counter, with repeat-reload mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 52 TIMA1.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 6 to 15 Reserved Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 53 Event Subscriber Port 0 Event Subscriber Port 1 18-31 Reserved For more details, see the TIMx chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 54: Device Analog Connections

    Supply/Battery Monitor A1_0:A1_7 A0_7 Temp Sense ADC1 GPAMP Output Supply/Battery Monitor GPAMP Internal signal to ADC0, ADC1, GPAMP_IN+ GPAMP GPAMP_OUT GPAMP_IN- Figure 8-1. Analog Connections Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 55: Input/Output Diagrams

    DOUT Peripheral 15 RSTN Driver Logic Unassigned Peripheral 01 Hi-Z Peripheral 15 RSTN PF != 0 PIPU PIPD SHUTDOWN RELEASE Figure 8-2. Superset Input/Output Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 56: Serial Wire Debug Interface

    Refer to Factory Constants chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 57: Identification

    The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 10.4) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 58: Applications, Implementation, And Layout

    Debug tool are optional, but SWCLK NRST must be Debug interface pulled high to VDD for the device to start. Figure 9-1. Basic Application Schematic Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 59: Device And Documentation Support

    10.1 Getting Started and Next Steps For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help with development, visit the Texas Instruments Arm Cortex-M0+ MCUs page.
  • Page 60: Tools And Software

    TI Arm Clang is included in Code Composer Studio. GNU Arm Embedded The MSPM0 SDK supports development using the open-source Arm GNU Toolchain Toolchain.Arm GCC is supported by Code Composer Studio (CCS). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 61: Documentation Support

    All trademarks are the property of their respective owners. 10.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 62: Mechanical, Packaging, And Orderable Information

    12 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2023 Initial Public Release Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107 MSPM0G3106 MSPM0G3105...
  • Page 63 PACKAGE OUTLINE RHB0032E VQFN - 1 mm max height SC AL E 3 .0 0 0 PLASTIC QUAD FLATPACK - NO LEAD PIN 1 INDEX AREA (0.1) SIDE WALL DETAIL OPTIONAL METAL THICKNESS 2 0 .0 0 0 1 MAX SEATING PLANE 0.05 0.08 C...
  • Page 64 4223442/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
  • Page 65 EXAMPLE STENCIL DESIGN RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.49) (0.845) (R0.05) TYP 32X (0.6) 32X (0.25) 28X (0.5) (0.845) SYMM (4.8) METAL SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X...
  • Page 66 DETAIL A A 2 0 TYPICAL 4226365/A 10/2020 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.
  • Page 67 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
  • Page 68 EXAMPLE STENCIL DESIGN DGS0028A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 28X (1.45) SYMM 28X (0.3) (R0.05) TYP 26X (0.5) SYMM (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 13X 4226365/A 10/2020 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
  • Page 69 DETAIL A A 2 0 TYPICAL 4226367/A 10/2020 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.
  • Page 70 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
  • Page 71 EXAMPLE STENCIL DESIGN DGS0020A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 20X (1.45) SYMM 20X (0.3) (R0.05) TYP SYMM (18X 0.5) (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 16X 4226367/A 10/2020 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
  • Page 72 PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2023 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) XMSM0G3105SRHBR ACTIVE VQFN 3000 Call TI Call TI -40 to 125 Samples XMSM0G3106SRHBR...
  • Page 73 PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2023 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
  • Page 74 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

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