Texas Instruments MSPM0G150 Series Manual
Texas Instruments MSPM0G150 Series Manual

Texas Instruments MSPM0G150 Series Manual

Mixed-signal microcontrollers

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1 Features

Core
– Arm
®
32-bit Cortex
®
protection unit, frequency up to 80 MHz
Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62 V to 3.6 V
Memories
– Up to 128KB of flash memory with error
correction code (ECC)
– Up to 32KB of SRAM with hardware parity
High-performance analog peripherals
– Two simultaneous sampling 12-bit 4-Msps
analog-to-digital converters (ADCs) with up to
17 external channels
14-bit effective resolution at 250-ksps with
hardware averaging
– One 12-bit 1-MSPS digital-to-analog converter
with integrated output buffer (DAC)
– Two zero-drift zero-crossover chopper op-amps
(OPA)
0.5-µV/°C drift with chopping
Integrated programmable gain stage, up to
32x
– One general-purpose amplifier (GPAMP)
– Three high-speed comparators (COMP) with 8-
bit reference DACs
32-ns propagation delay in high-speed
mode
Support low-power mode operation down to
<1 µA
– Programmable analog connections between
ADC, OPAs, COMP and DAC
– Configurable 1.4-V or 2.5-V internal shared
voltage reference (VREF)
– Integrated temperature sensor
Optimized low-power modes
– RUN: 96 µA/MHz (CoreMark)
– SLEEP: 458 µA at 4 MHz
– STOP: 47 µA at 32 kHz
– STANDBY: 1.5 µA with RTC and SRAM
retention
– SHUTDOWN: 78 nA with IO wake-up capability
Intelligent digital peripherals
– 7-channel DMA controller
– Math accelerator supports DIV, SQRT, MAC
and TRIG computations
– Seven timers supports up to 22 PWM channels
One 16-bit general-purpose timer
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
MSPM0G150x Mixed-Signal Microcontrollers
-M0+ CPU with memory
MSPM0G1507, MSPM0G1506, MSPM0G1505
SLASEW9B – FEBRUARY 2023 – REVISED AUGUST 2023
One 16-bit general-purpose timer supports
QEI
Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
One 32-bit high-resolution general-purpose
timer
Two 16-bit advanced timers with deadband
support up to 12 PWM channels
– Two window-watchdog timers
– RTC with alarm and calendar mode
Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
2
– Two I
C interfaces support up to FM+ (1
Mbit/s), SMBus/PMBus, and wakeup from
STOP mode
– Two SPIs, one SPI supports up to 32 Mbits/s
Clock system
– Internal 4- to 32-MHz oscillator with up to
±1.2% accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80 MHz
– Internal 32-kHz low-frequency oscillator
(LFOSC) with ±3% accuracy
– External 4- to 48-MHz crystal oscillator (HFXT)
– External 32-kHz crystal oscillator(LFXT)
– External clock input
Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
– True random number generator (TRNG)
– AES encryption with 128 or 256-bit key
Flexible I/O features
– Up to 60 GPIOs
Two 5-V tolerant IOs
Two high-drive IOs with 20-mA drive
strength
Development support
– 2-pin serial wire debug (SWD)
Package options
– 64-pin LQFP
– 48-pin LQFP, VQFN
– 32-pin VQFN
– 28-pin VSSOP
– 24-pin VQFN.
Family members (also see
– MSPM0G1505: 32KB flash, 16KB RAM
– MSPM0G1506: 64KB flash, 32KB RAM
– MSPM0G1507: 128KB flash, 32KB RAM
Development kits and software (also see
and
Software)
Device
Comparison)
Tools

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Summary of Contents for Texas Instruments MSPM0G150 Series

  • Page 1: Features

    MSPM0G1507, MSPM0G1506, MSPM0G1505 SLASEW9B – FEBRUARY 2023 – REVISED AUGUST 2023 MSPM0G150x Mixed-Signal Microcontrollers • One 16-bit general-purpose timer supports 1 Features • Core • Two 16-bit general-purpose timers support low-power operation in STANDBY mode – Arm ® 32-bit Cortex ®...
  • Page 2: Applications

    See MSP430™ System-Level ESD Considerations for more information. The principles in this application note are applicable to MSPM0 MCUs. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 3: Functional Block Diagram

    VCORE, NRST PD1, CPU/DMA ACCESS to OPA0 and OPA1, respectively ROSC PD1/PD0, CPU/DMA ACCESS CLK_OUT, FCC_IN PD0, CPU/DMA ACCESS Figure 4-1. MSPM0G150x Functional Block Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 4: Table Of Contents

    8.2 Operating Modes............10.8 Glossary..............79 8.3 Power Management Unit (PMU)....... 11 Mechanical, Packaging, and Orderable 8.4 Clock Module (CKM)..........57 Information..............8.5 DMA................12 Revision History............8.6 Events............... Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 5: Device Comparison

    The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section For more information about the device name, see Section 10.2 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 6: Pin Configuration And Functions

    For full descriptions of the pin functions, see the Pin Attributes and Signal Descriptions sections. 6.1 Pin Diagrams Power Reset High-Speed I/O (HSIO) 5-V Tolerant Open-Drain I/O (ODIO) High-Drive I/O (HDIO) Figure 6-1. Pin Diagram Color Coding Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 7 PA30 PA20 / SWCLK PA29 PB17 / A1_4 PA28 PB18 / A1_5 PB19 / A1_6 PA0 / FCC_IN Figure 6-2. 64-Pin PM (LQFP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 8 PA12 / FCC_IN PA4 / LFCLK_IN / LFXOUT PB16 PA5 / HFXIN / FCC_IN PB15 PA6 / HFCLK_IN / HFXOUT Figure 6-3. 48-Pin PT (LQFP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 9 PA4 / LFCLK_IN / LFXOUT PA12 / FCC_IN PA5 / HFXIN / FCC_IN PB16 PA6 / HFCLK_IN / HFXOUT PB15 Thermal pad Figure 6-4. 48-Pin RGZ (VQFN) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 10 PA15 / A1_0 PA3 / LFXIN PA14 / CLK_OUT / A0_12 PA13 PA4 / LFCLK_IN / LFXOUT Thermal pad Figure 6-5. 32-Pin RHB (VQFN) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 11 PA4 / LFCLK_IN / LFXOUT PA15 / A1_0 PA14 / CLK_OUT / A0_12 PA11 PA10 / CLK_OUT PA9 / RTC_OUT / CLK_OUT Figure 6-6. 28-Pin DGS28 (VSSOP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 12 Thermal Figure 6-7. 24-Pin RGE (VQFN) (Top View) Note For full pin configuration and functions for each package option, refer to Pin Attributes Signal Descriptions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 13: Pin Attributes

    Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 14 TIMA1_C1 [4] / TIMA0_C2N [5] COMP0_OUT [2] / CLK_OUT [3] / TIMG8_C0 [4] / TIMA0_C2 [5] / Standard TIMG8_IDX [6] / TIMG7_C1 [7] / TIMA0_C1 [8] Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 15 UART3_TX [2] / TIMA0_C2 [3] / PB12 Standard TIMA_FAL1 [4] / TIMA0_C1 [5] UART3_RX [2] / TIMA0_C3 [3] / PB13 Standard TIMG12_C0 [4] / TIMA0_C1N [5] Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 16 UART2_RX [2] / TIMG8_C1 [3] / A0_7 / UART1_RTS [4] / TIMA0_C1 [5] / PA22 GPAMP_OUT / Standard CLK_OUT [6] / TIMA0_C0N [7] / OPA0_OUT TIMG6_C1 [8] Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 17 Table 6-2. Digital IO Features by IO Type DRIVE INVERSION HYSTERESIS PULLUP PULLDOWN WAKEUP IO STRUCTURE STRENGTH CONTROL CONTROL RESISTOR RESISTOR LOGIC CONTROL Standard-drive Standard-drive with wake High-drive High-speed Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 18: Signal Descriptions

    Digital low-frequency clock input LFXIN – Input for low-frequency crystal oscillator LFXT LFXOUT Output of low-frequency crystal oscillator LFXT External resistor used for improving oscillator ROSC accuracy Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 19 Serial wire debug data input/output FCC_IN Frequency clock counter input GPAMP_IN+ GPAMP noninverting terminal input General- Purpose GPAMP_IN- GPAMP inverting terminal input Amplifier GPAMP_OUT GPAMP output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 20 – – General-purpose digital I/O PA30 – – – – General-purpose digital I/O General-purpose digital I/O with wake up from PA31 – – – SHUTDOWN Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 21 General-purpose digital I/O PB27 – – – – General-purpose digital I/O I2C0_SCL I2C0 serial clock I2C0_SDA I2C0 serial data I2C1_SCL I2C1 serial clock I2C1_SDA I2C1 serial data Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 22 Power VCORE Regulated core power supply output QFN package exposed thermal pad. TI QFN Pad – – recommends connection to V RTC_OUT RTC clock output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 23 SPI1 clock signal input – SPI peripheral mode SPI1_SCK Clock signal output – SPI controller mode SPI1_POCI SPI1 controller in/peripheral out SPI1_PICO SPI1 controller out/peripheral in System NRST Reset input active low Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 24 General purpose timer 7 CCR1 capture input/ TIMG7_C0 compare output General purpose timer 7 CCR1 capture input/ TIMG7_C1 compare output General purpose timer 8 CCR0 capture input/ TIMG8_C0 compare output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 25 Advanced control timer 0 CCR0 compare output TIMA0_C0N (inverting) Advanced control timer 0 CCR1 capture input/ TIMA0_C1 compare output Advanced control timer 0 CCR1 compare output TIMA0_C1N (inverting) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 26 Advanced control timer 0 CCR3 compare output TIMA1_C0N (inverting) Advanced control timer 1 CCR1 capture input/ TIMA1_C1 compare output Advanced control timer 1 CCR1 compare output TIMA1_C1N (inverting) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 27 UART1 "request to send" flow control output UART2_TX UART2 transmit data UART2_RX UART2 receive data UART2_CTS UART2 "clear to send" flow control input UART2_RTS UART2 "request to send" flow control output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 28 When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 29: Connections For Unused Pins

    Section 9.1 Any unused pin with a function that is shared with general-purpose I/O should follow the "PAx and PBx" unused pin connection guidelines. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 30: Specifications

    MCLK, CPUCLK frequency with 2 flash wait states MCLK, CPUCLK frequency with 1 flash wait state MCLK (PD1 bus clock) MCLK, CPUCLK frequency with 0 flash wait states Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 31: Thermal Information

    Junction-to-board thermal resistance 41.3 °C/W θJB VSSOP-28 (DGS28) Ψ Junction-to-top characterization parameter °C/W Ψ Junction-to-board characterization parameter 41.0 °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 32 Junction-to-case (bottom) thermal resistance °C/W θJC(bot) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 33: Supply Current Characteristics

    STANDBY Mode LFCLK=LFXT, STOPCLKSTBY=0, 6.91 STBY0 RTC enabled LFCLK=LFOSC, STOPCLKSTBY=1, 15.5 RTC enabled 32kHz µA LFCLK=LFXT, STOPCLKSTBY=1, 15.5 STBY1 RTC enabled LFCLK=LFXT, STOPCLKSTBY=1, 15.6 GPIOA enabled Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 34: Power Supply Sequencing

    Device operating in RUN, SLEEP, or STOP mode. 7.6.2 Power Supply Ramp Figure 7-1 gives the relationship of POR- POR+, BOR0-, and BOR0+ during power-up and power-down. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 35: Flash Memory Characteristics

    Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 36: Timing Characteristics

    The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 37: Clock Specifications

    , after which the target accuracy is SYSOSC settle,SYSOSC settle,SYSOSC achieved. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 38 (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT Low frequency crystal oscillator (LFXT) LFXT frequency 32768 LFXT LFXT duty cycle LFXT Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 39 Manual.Current consumption increases with higher RSEL and start up time is decreases with higher RSEL. The digital clock input (HFCLK_IN) accepts a logic level square wave clock. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 40: Digital Io

    ≤130 °C VDD≥2.7V, DRV=1, |I =20mA ,max VDD-0.4 VDD≥1.71V, DRV=1, |I =10mA ,max HDIO VDD≥2.7V, DRV=0, |I =6mA ,max VDD-0.4 VDD≥1.71V, DRV=0, |I =2mA ,max Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 41 VDD ≥ 2.7V, DRV = 0, CL= 20pF ODIO VDD ≥ 1.71V, FM , CL= 20pF - 100pF All output ports 0.3 × Output rise/fall time VDD ≥ 1.71V except ODIO Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 42: Analog Mux Vboost

    R– All external reference specifications are measured with V = VREF+ = VDD = 3.3V and V = VREF- = VSS = 0V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 43 Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: 1. Tau = (R ) × C × (C 2. K= ln(2 /Settling error) – ln((C Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 44: Temperature Sensor

    A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable The VREF module should only be enabled when C is connected and should not be enabled otherwise. VREF Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 45: Comparator (Comp)

    Output voltage range No load, Vref = VDD, DATA = 0x0 0.005 0.05 Output voltage range No load, Vref = VDD, DATA = 0xFFF VDD-0.05 -0.01 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 46 Turn on time from off state (VREF ready) DATA = 0xFFF, Error < ±2 LSB, Vref = internal reference µs ON,12b DATA = 0x1EC->0xFFF->0x1EC, Error< ±2 LSB, Vref = Full scale settling time µs S(FS) internal reference Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 47: Gpamp

    GPAMP disable time disable Cycles = 200 pF, Vstep = 0.3V to VDD - GPAMP settling time Noninverting, unity gain µs SETTLE 0.3V, 0.1%, ENABLE = 0x1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 48: Opa

    Input capacitance Common mode Open-loop voltage gain, DC = 20kΩ to GND, 0.3<Vo<VDD-0.3 GBW = 0x0 phase margin = 40pF degree GBW = 0x1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 49 GAIN = 0x2 –1.0% –3 +1.0% inverting gain GAIN = 0x3 –1.2% –7 1.2% GAIN = 0x4 –1.5% –15 1.5% GAIN = 0x5 –2.7% –31 2.7% Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 50: I2C

    (unless otherwise noted) PARAMETERS TEST CONDITIONS UNIT AGFSELx = 0 AGFSELx = 1 Pulse duration of spikes suppressed by input filter AGFSELx = 2 AGFSELx = 3 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 51: Spi

    POCI input data setup time 1.62 < VDD < 2.7V, no delayed sampling SU.CI POCI input data hold time HD.CI PICO output data valid time VALID.CO Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 52 CS, DIS CS, ACC VALID,CO VALID,CO PICO PICO Controller Mode, SPH = 0 Controller Mode, SPH = 1 Figure 7-6. SPI timing diagram - Controller Mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 53: Uart

    7.23.1 TRNG Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT TRNG TRNG active current TRNG clock = 20MHz µA IACT Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 54: Emulation And Debug

    51.2 µs LAT256 20MHz 7.24 Emulation and Debug 7.24.1 SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT SWD frequency Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 55: Detailed Description

    OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be reconfigured to the desired settings by application software. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 56 Core Functions Flash SRAM UART3 SPI0, SPI1 Peripherals MATHACL TIMA0, TIMA1 TIMG6, TIMG7 TIMG12 TIMG0, TIMG8 UART0, UART1, UART2 Peripherals I2C0, I2C1 GPIOA, GPIOB WWDT0, WWDT1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 57: Power Management Unit (Pmu)

    CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode • ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 58: Dma

    SPI0 Publisher 1 ADC1 Publisher 2 SPI0 Publisher 2 For more details, see the DMA chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 59: Events

    For more information about the memory region detail, see the Platform Memory Map section in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 60 Table 8-5. Peripherals Summary Peripheral Name Base Address Size COMP0 0x40008000 0x2000 COMP1 0x4000A000 0x2000 COMP2 0x4000C000 0x2000 DAC_OUT 0x40018000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 61 0x40558000 0x1000 TIMA0 0x40860000 0x2000 TIMA1 0x40862000 0x2000 TIMG6 0x40868000 0x2000 TIMG7 0x4086A000 0x2000 TIMG12 0x40870000 0x2000 Aliased region of ADC0 and ADC1 memory-mapped registers Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 62: Flash Memory

    Hardware ECC protection (encode and decode) with single bit error correction and double-bit error detection • In-circuit program and erase operations supported across the entire recommended supply range • Small 1kB sector sizes (minimum erase resolution of 1kB) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 63: Sram

    – Configurable internal reference voltage of 1.4V and 2.5V (requires decoupling capacitor on VREF+/- pins) – MCU supply voltage (VDD) – External reference supplied to the ADC through the VREF+/- pins • Operates in RUN, SLEEP, and STOP modes Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 64: Temperature Sensor

    The comparator peripheral in the device compares the voltage levels on two inputs terminals and provides a digital output based on this comparison. It supports the following key features: • Programmable hysteresis • Programmable reference voltage: Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 65 For more information about device analog connections, see Section 8.28. For more details, see the COMP chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 66: Dac

    N-MUX INPUTS MSEL M-MUX INPUTS Open Open Open OPA1_IN0+ OPA1_IN0- OPA1_IN1- OPA1_IN1+ OPA1_IN1- DAC_OUT / OPA1_IN2+ OPA0_RBOT DAC_OUT / OPA1_IN2+ DAC8.1_OUT RTAP OPA0_RTOP VREF RTOP OPA0_RTOP Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 67: Gpamp

    CRC module include: • Support for 16-bit CRC based on CRC16-CCITT • Support for 32-bit CRC based on CRC32-ISO3309 • Support for bit reversal Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 68: Uart

    Support analog and digital glitch filter for input signal glitch suppression • 8-entry transmit and receive FIFOs For more details, see the I2C chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 69: Spi

    16-bit up, down, up-down or down-up counter, with repeat-reload mode Only SPI signals on HSIO pins support data rate > 16 Mbits/s; see the Pin Diagrams section for HSIO pins. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 70 TIMA1.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 6 to 15 Reserved Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 71 Event Subscriber Port 0 Event Subscriber Port 1 18-31 Reserved For more details, see the TIMx chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 72: Device Analog Connections

    Figure 8-1. Device Analog Connection Note Enabling DAC_OUT connects to PA15 therefore it is not recommended to have any external signal on PA15 when using DAC_OUT. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 73: Input/Output Diagrams

    DOUT Peripheral 15 RSTN Driver Logic Unassigned Peripheral 01 Hi-Z Peripheral 15 RSTN PF != 0 PIPU PIPD SHUTDOWN RELEASE Figure 8-2. Superset Input/Output Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 74: Serial Wire Debug Interface

    Please refer to Factory Constants chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for more information. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 75: Identification

    The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 10.4) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 76: Applications, Implementation, And Layout

    Debug tool are optional, but SWCLK NRST must be Debug interface pulled high to VDD for the device to start. Figure 9-1. Basic Application Schematic Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 77: Device And Documentation Support

    10.1 Getting Started and Next Steps For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help with development, visit the Texas Instruments Arm Cortex-M0+ MCUs page.
  • Page 78: Tools And Software

    GNU Arm Embedded The MSPM0 SDK supports development using the open-source Arm GNU Toolchain Toolchain. Arm GCC is supported by Code Composer Studio IDE (CCS). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 79: Documentation Support

    All trademarks are the property of their respective owners. 10.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 80: Mechanical, Packaging, And Orderable Information

    Page • Corrected pin diagram for 20-pin device......................• Corrected the pin attributes descriptions for 24-pin RGE................. • Corrected the signal descriptions for 24-pin RGE.................... Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505...
  • Page 81 PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2023 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) XMSM0G1505SRGER ACTIVE VQFN 3000 Call TI Call TI -40 to 125 Samples XMSM0G1506SRGER...
  • Page 82 PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2023 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2...
  • Page 83 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

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