Texas Instruments MSPM0G310 Series Manual
Texas Instruments MSPM0G310 Series Manual

Texas Instruments MSPM0G310 Series Manual

Automotive mixed-signal microcontrollers with can-fd interface
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MSPM0G310x Automotive Mixed-Signal Microcontrollers With CAN-FD Interface

1 Features

Qualified for automotive applications
Core
– Arm
®
32-bit Cortex
®
protection unit, frequency up to 80 MHz
Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62 V to 3.6 V
Memories
– Up to 128KB of flash memory with built-in error
correction code (ECC)
– Up to 32KB of SRAM with hardware parity
High-performance analog peripherals
– Two simultaneous sampling 12-bit 4-Msps
analog-to-digital converters (ADCs) with up to
11 external channels
14-bit effective resolution at 250-ksps with
hardware averaging
– One general-purpose amplifier (GPAMP)
– Configurable 1.4-V or 2.5-V internal shared
voltage reference (VREF)
– Integrated temperature sensor
– Integrated supply monitor
Optimized low-power modes
– RUN: 96 µA/MHz (CoreMark)
– SLEEP: 467 µA at 4 MHz
– STOP: 46 µA at 32 kHz
– STANDBY: 1.5 µA with RTC and SRAM
retention
– SHUTDOWN: 80 nA with IO wakeup capability
Intelligent digital peripherals
– 7-channel DMA controller
– Two 16-bit advanced control timers support
dead band insertion and fault handling
– Seven timers supporting up to 22 PWM
channels
One 16-bit general purpose timer
One 16-bit general purpose timer supports
QEI
Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
One 32-bit general-purpose timer
Two 16-bit advanced timers with deadband
– Two window-watchdog timers
– RTC with alarm and calendar mode
Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
-M0+ CPU with memory
MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1
2
– Two I
C interfaces supporting up to FM+
(1 Mbit/s), SMBus, PMBus, and wakeup from
STOP mode
– Two SPIs, one SPI supports up to 32 Mbits/s
– One Controller Area Network (CAN) interface
supports CAN 2.0 A or B and CAN-FD
Clock system
– Internal 4- to 32-MHz oscillator with up to
±1.2% accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80 MHz
– Internal 32-kHz oscillator (LFOSC) with ±3%
accuracy
– External 4- to 48-MHz crystal oscillator (HFXT)
– External 32-kHz crystal oscillator(LFXT)
– External clock input
Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
– True random number generator (TRNG)
– AES encryption with 128 or 256-bit key
Flexible I/O features
– Up to 28 GPIOs
Two 5-V tolerant IOs
Two high-drive IOs with 20-mA drive
strength
Development support
– 2-pin serial wire debug (SWD)
Package options
– 64-pin LQFP
– 48-pin LQFP , VQFN
– 32-pin VQFN
– 28-pin VSSOP
– 24-pin VQFN
– 20-pin VSSOP
Family members (also see
– MSPM0G3105: 32KB flash, 16KB RAM
– MSPM0G3106: 64KB flash, 32KB RAM
– MSPM0G3107: 128KB flash, 32KB RAM
Development kits and software (also see
and
Software)
LP-MSPM0G3507 LaunchPad
kit
– MSP Software Development Kit (SDK)
Automotive qualification
– AEC-Q100 Grade 1 (-40°C to 125°C)
– 24, 32, and 48-pin QFN with wettable flanks
option
SLASF86 – OCTOBER 2023
Device
Comparison)
Tools
development

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Summary of Contents for Texas Instruments MSPM0G310 Series

  • Page 1: Features

    MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 SLASF86 – OCTOBER 2023 MSPM0G310x Automotive Mixed-Signal Microcontrollers With CAN-FD Interface – Two I C interfaces supporting up to FM+ 1 Features (1 Mbit/s), SMBus, PMBus, and wakeup from • Qualified for automotive applications STOP mode • Core –...
  • Page 2: Applications

    See MSP430™ System-Level ESD Considerations for more information. The principles in this application note are applicable to MSPM0 MCUs. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 3: Functional Block Diagram

    LFXIN, LFXOUT VDD, VSS HFXIN, HFXOUT VCORE, NRST PD1, CPU/DMA ACCESS ROSC PD1/PD0, CPU/DMA ACCESS CLK_OUT, FCC_IN PD0, CPU/DMA ACCESS Figure 4-1. MSPM0G310x Functional Block Diagram Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 4: Table Of Contents

    8.3 Power Management Unit (PMU)....... 10.8 Glossary..............69 8.4 Clock Module (CKM)..........49 11 Mechanical, Packaging, and Orderable 8.5 DMA................Information..............8.6 Events............... 12 Revision History ............Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 5: Device Comparison

    The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, Section For more information about the device name, see Section 10.2. 24,32 and 48 -pin VQFN package available with wettable flanks. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 6: Pin Configuration And Functions

    PA30 PA20 / SWCLK PA29 PB17 / A1_4 PA28 PB18 / A1_5 PB19 / A1_6 PA0 / FCC_IN Figure 6-2. 64-Pin PM (LQFP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 7 PA12 / FCC_IN PA4 / LFCLK_IN / LFXOUT PB16 PA5 / HFXIN / FCC_IN PB15 PA6 / HFCLK_IN / HFXOUT Figure 6-3. 48-Pin PT (LQFP) (Top View) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 8 PA4 / LFCLK_IN / LFXOUT PA12 / FCC_IN PA5 / HFXIN / FCC_IN PB16 PA6 / HFCLK_IN / HFXOUT PB15 Thermal pad Figure 6-4. 48-Pin RGZ (VQFN) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 9 PA4 / LFCLK_IN / LFXOUT PA15 / A1_0 PA14 / CLK_OUT / A0_12 PA11 PA9 / RTC_OUT / CLK_OUT PA10 / CLK_OUT Figure 6-6. 28-Pin DGS28(VSSOP) (Top View) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 10 Figure 6-8. 20-Pin DGS20 (VSSOP) (Top View) Note For the full pin configuration and description of the functions for each package option, see Attributes Signal Descriptions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 11: Pin Attributes

    UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] / TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] / 50 14 – – – – Standard TIMA1_C0 [8] Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 12 UART0_RTS [2] / SPI1_CS2 [3] / I2C1_SCL [4] / PA15 A1_0 TIMA1_C0 [5] / TIMG8_IDX [6] / TIMA1_C0N [7] / 30 19 18 – Standard TIMA0_C2 [8] Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 13 UART3_TX [2] / SPI1_CS0 [3] / TIMG8_C0 [4] / PA26 A0_1 / GPAMP_IN+ 30 46 30 Standard TIMA_FAL0 [5] / CAN_TX [6] / TIMG7_C0 [7] Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 14: Signal Descriptions

    ADC1 analog input 7 BSL_invoke Input pin used to invoke bootloader BSLSCL – Default I C BSL clock BSL (I BSLSDA – Default I C BSL data Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 15 Serial wire debug data input/output FCC_IN Frequency clock counter input GPAMP_IN+ GPAMP noninverting terminal input General- Purpose GPAMP_IN- GPAMP inverting terminal input Amplifier GPAMP_OUT 18 GPAMP output Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 16 General-purpose digital I/O PA30 – – – – – General-purpose digital I/O General-purpose digital I/O with wake up PA31 – – – – from SHUTDOWN Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 17 PB27 – – – – – General-purpose digital I/O I2C0_SCL I2C0 serial clock I2C0_SDA I2C0 serial data I2C1_SCL I2C1 serial clock I2C1_SDA I2C1 serial data Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 18 VCORE Regulated core power supply output QFN package exposed thermal pad. TI QFN Pad – – – recommends connection to V RTC_OUT RTC clock output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 19 Clock signal output – SPI controller mode SPI1_POCI – SPI1 controller in/peripheral out SPI1_PICO SPI1 controller out/peripheral in System NRST Reset input active low Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 20 General purpose timer 7 CCR1 capture TIMG7_C0 input/ compare output General purpose timer 7 CCR1 capture TIMG7_C1 input/ compare output General purpose timer 8 CCR0 capture TIMG8_C0 input/ compare output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 21 TIMA0_C0N input/compare output (inverting) Advanced control timer 0 CCR1 capture TIMA0_C1 input/ compare output Advanced control timer 0 CCR1 capture TIMA0_C1N input/ compare output (inverting) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 22 (inverting) Advanced control timer 1 CCR1 capture TIMA1_C1 input/ compare output Advanced control timer 1 CCR1 capture TIMA1_C1N input/ compare output (inverting) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 23 UART2 transmit data UART2_RX UART2 receive data UART2_CTS – UART2 "clear to send" flow control input UART2_RTS – UART2 "request to send" flow control output Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 24 When using VREF+/- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 25: Connections For Unused Pins

    Section 9.1. Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx and PBx" unused pin connection guidelines. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 26: Specifications

    Capacitor connected between VDD and VSS µF (1) (2) Capacitor connected between VCORE and VSS VCORE Ambient temperature, Q version –40 °C Max junction temperature, Q version °C Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 27: Thermal Information

    Junction-to-board thermal resistance 41.3 °C/W θJB VSSOP-28 (DGS28) Ψ Junction-to-top characterization parameter °C/W Ψ Junction-to-board characterization parameter 41.0 °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 28 Junction-to-case (bottom) thermal resistance °C/W θJC(bot) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 29: Supply Current Characteristics

    32kHz STOP2 ULPCLK=LFCLK STANDBY Mode LFCLK=LFXT, STOPCLKSTBY=0, STBY0 RTC enabled LFCLK=LFOSC, STOPCLKSTBY=1, RTC enabled 32kHz µA LFCLK=LFXT, STOPCLKSTBY=1, STBY1 RTC enabled LFCLK=LFXT, STOPCLKSTBY=1, GPIOA enabled Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 30: Power Supply Sequencing

    Device operating in RUN, SLEEP, or STOP mode. 7.6.2 Power Supply Ramp Figure 7-1 shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 31: Flash Memory Characteristics

    Maximum number of write operations allowed per word line before the word line must be erased. If additional writes to the same word line are required, a sector erase is required once the maximum number of write operations per word line is reached. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback...
  • Page 32: Timing Characteristics

    The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 33: Clock Specifications

    The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an internal reference resistor when using the FCL. See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback...
  • Page 34 7.9.4 Low Frequency Crystal/Clock over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT Low frequency crystal oscillator (LFXT) LFXT frequency 32768 LFXT Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 35 Manual.Current consumption increases with higher RSEL and start up time is decreases with higher RSEL. The digital clock input (HFCLK_IN) accepts a logic level square wave clock. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 36: Digital Io

    ≤130 °C VDD≥2.7V, DRV=1, |I =20mA ,max VDD-0.4 VDD≥1.71V, DRV=1, |I =10mA ,max HDIO VDD≥2.7V, DRV=0, |I =6mA ,max VDD-0.4 VDD≥1.71V, DRV=0, |I =2mA ,max Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 37 VDD ≥ 1.71V, DRV = 0, CL= 20pF HDIO VDD ≥ 2.7V, DRV = 0, CL= 20pF ODIO VDD ≥ 1.71V, FM , CL= 20pF - 100pF Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 38: Analog Mux Vboost

    Power supply rejection ratio, AC ΔVDD = 0.1 V at 1 kHz Internal reference, V = VREF = 2.5V ADC Wakeup Time Assumes internal reference is active wakeup Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 39 Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate All external reference specifications are measured with V = VREF+ = VDD and V = VSS = 0V, external 1uF cap on VREF+ pin. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 40: Temperature Sensor

    BUFCONFIG = {0, 1}, No load µA VREF VREF output drive strength Drive strength supported on VREF+ device pin µA Drive VREF short circuit current Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 41: Gpamp

    Common mode rejection ratio, DC range CHOP = 0x1 f = 1 kHz Input voltage noise density Noninverting, unity gain nV/√Hz f = 10 kHz Input resistance 0.65 kΩ Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 42: I2C

    Hold time (repeated) START 0.26 HD,STA LOW period of the SCL clock High period of the SCL clock 0.26 HIGH Setup time for a repeated 0.26 SU,STA START Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 43: Spi

    Peripheral mode with High speed IO Clock max speed >= 64MHz SPI clock frequency 2.7 < VDD < 3.6V Peripheral mode with High speed IO SCK Duty Cycle Controller Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 44 Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 45: Uart

    UART BITCLK clock frequency(equals UART in Power Domain1 BITCLK baud rate in MBaud) BITCLK clock frequency(equals UART in Power Domain0 BITCLK baud rate in MBaud) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 46: Timx

    51.2 µs LAT256 20MHz 7.21 Emulation and Debug 7.21.1 SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT SWD frequency Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 47: Detailed Description

    OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 48 Core Functions Flash SRAM UART3 SPI0, SPI1 Peripherals MCAN0 TIMA0, TIMA1 TIMG6, TIMG7 TIMG12 TIMG0, TIMG8 UART0, UART1, UART2 Peripherals I2C0, I2C1 GPIOA, GPIOB WWDT0, WWDT1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 49: Power Management Unit (Pmu)

    MFPCLK: 4-MHz fixed mid-frequency precision clock, available in RUN, SLEEP, and STOP modes • LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 50: Dma

    The event manager transfers digital events from one entity (for example, a peripheral) to another (for example, a second peripheral, the DMA, or the CPU). The event manager implements event transfer through a defined set Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 51: Memory

    128KB-8B ECC Corrected 0x0000.0000 to 0x0000.0000 to 0x0000.0000 to 0x0000.7FF8 0x0000.FFF8 0x0001.FFF8 Code (Flash) 0x0040.0000 to 0x0040.0000 to 0x0040.0000 to ECC Uncorrected 0x0040.7FF8 0x0040.FFF8 0x0041.FFF8 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 52 0x40082000 0x2000 TIMG0 0x40084000 0x2000 TIMG8 0x40090000 0x2000 0x40094000 0x2000 GPIO0 0x400A0000 0x2000 GPIO1 0x400A2000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 53 0x40558000 0x1000 TIMA0 0x40860000 0x2000 TIMA1 0x40862000 0x2000 TIMG6 0x40868000 0x2000 TIMG7 0x4086A000 0x2000 TIMG12 0x40870000 0x2000 Aliased region of ADC0 and ADC1 memory-mapped registers Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 54: Flash Memory

    (devices with 32KB support 100,000 cycles on the entire flash memory) For a complete description of the flash memory, see the NVM chapter of the technical reference manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 55: Sram

    – MCU supply voltage (VDD) – External reference supplied to the ADC through the VREF+ and VREF- pins • Operates in RUN, SLEEP, and STOP modes Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 56: Temperature Sensor

    The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features: • Software selectable chopper stabilization Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 57: Trng

    – Programmable baud rate generation with oversampling by 16, 8 or 3 – Local Interconnect Network (LIN) mode support • Separated transmit and receive FIFOs support DAM data transfer Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 58: I2C

    MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Only SPI signals on HSIO pins support data rate > 16 Mbits/s; see the Pin Diagrams section for HSIO pins. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 59: Can-Fd

    The timer peripherals in these devices support the following key features, for specific configuration see Table 8-9: Specific features for the general-purpose timer (TIMGx) include: Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 60 TIMA1.TRIG0 TIMA1.TRIG0 TIMA1.TRIG0 TIMA1.TRIG0 TIMA1.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG6.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG7.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG12.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 61 Event Subscriber Port 0 Event Subscriber Port 1 18-31 Reserved For more details, see the TIMx chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 62: Device Analog Connections

    Supply/Battery Monitor A1_0:A1_7 A0_7 Temp Sense ADC1 GPAMP Output Supply/Battery Monitor GPAMP Internal signal to ADC0, ADC1, GPAMP_IN+ GPAMP GPAMP_OUT GPAMP_IN- Figure 8-1. Analog Connections Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 63: Input/Output Diagrams

    DOUT Peripheral 15 RSTN Driver Logic Unassigned Peripheral 01 Hi-Z Peripheral 15 RSTN PF != 0 PIPU PIPD SHUTDOWN RELEASE Figure 8-2. Superset Input/Output Diagram Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 64: Serial Wire Debug Interface

    Refer to Factory Constants chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 65: Identification

    The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 10.4) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 66: Applications, Implementation, And Layout

    Debug tool are optional, but SWCLK NRST must be Debug interface pulled high to VDD for the device to start. Figure 9-1. Basic Application Schematic Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 67: Device And Documentation Support

    10.1 Getting Started and Next Steps For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help with development, visit the Texas Instruments Arm Cortex-M0+ MCUs page.
  • Page 68: Tools And Software

    GNU Arm Embedded The MSPM0 SDK supports development using the open-source Arm GNU Toolchain Toolchain. Arm GCC is supported by Code Composer Studio IDE (CCS). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 69: Documentation Support

    All trademarks are the property of their respective owners. 10.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 70: Mechanical, Packaging, And Orderable Information

    12 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2023 Initial Release Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 71 PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2023 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) XM0G3107QPMRQ1 ACTIVE LQFP 1000 Call TI Call TI -40 to 125 Samples XM0G3107QRGERQ1...
  • Page 72 PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2023 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF MSPM0G3107-Q1 : •...
  • Page 73 GENERIC PACKAGE VIEW RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204104/H...
  • Page 74 GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 5 x 5, 0.5 mm pitch Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com...
  • Page 75 PACKAGE OUTLINE PM0064A LQFP - 1.6 mm max height SCALE 1.400 PLASTIC QUAD FLATPACK PLASTIC QUAD FLATPACK 10.2 NOTE 3 PIN 1 ID 10.2 12.2 11.8 NOTE 3 0.27 60X 0.5 0.17 4X 7.5 0.08 C A B (0.13) TYP SEATING PLANE 0.08 0.08...
  • Page 76 SOLDER MASK DETAILS 4215162/A 03/2017 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004). www.ti.com...
  • Page 77 EXAMPLE STENCIL DESIGN PM0064A LQFP - 1.6 mm max height PLASTIC QUAD FLATPACK SYMM 64X (1.5) 64X (0.3) SYMM 60X (0.5) (11.4) (R0.05) TYP (11.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X 4215162/A 03/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
  • Page 78 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

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