Mailbox Interrupt Mask Register (Mbimr) - Renesas H8S Series Hardware Manual

Section 15 Controller Area Network (HCAN)

15.3.12 Mailbox Interrupt Mask Register (MBIMR)

The mailbox interrupt mask register (MBIMR) is a 16-bit register that controls the enabling or
disabling of individual mailbox (buffer) interrupt requests.
Bit Bit Name
15 MBIMR7
14 MBIMR6
13 MBIMR5
12 MBIMR4
11 MBIMR3
10 MBIMR2
9 MBIMR1
8 MBIMR0
7 MBIMR15
6 MBIMR14
5 MBIMR13
4 MBIMR12
3 MBIMR11
2
MBIMR10
1 MBIMR9
0 MBIMR8
Rev. 6.00 Mar 15, 2006 page 404 of 570
REJ09B0211-0600
Initial Value R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Description
Mailbox Interrupt Mask (MBIMRx)
When MBIMRn (n = 1 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When set
to 1, the interrupt request is masked.
The interrupt source in a transmit mailbox is TXPR
clearing caused by transmission end or
transmission cancellation. The interrupt source in a
receive mailbox is RXPR setting on reception end.