Embedded Sram; Flash Memory Overview; Bit Banding - ST STM32F446 Series Reference Manual

2.2.3

Embedded SRAM

The STM32F446xx feature 4 Kbytes of backup SRAM (see
domain) plus 128 Kbytes of system SRAM.
The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
Read and write operations are performed at CPU speed with 0 wait state. The embedded
SRAM is divided into up to two blocks:
•
SRAM1 and SRAM2 mapped at address 0x2000 0000 and accessible by all AHB
masters.
The AHB masters support concurrent SRAM accesses (from the USB OTG HS): for
instance, the USB OTG HS can read/write from/to SRAM2 while the CPU is reading/writing
from/to SRAM1.
The CPU can access the SRAM1 and SRAM2 through the System Bus or through the I-
Code/D-Code buses when boot from SRAM is selected or when physical remap is selected
(Section 8.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP)
controller). To get the max performance on SRAM execution, physical remap should be
selected (boot or software selection).
2.2.4

Flash memory overview

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms. It accelerates code execution with a system of instruction
prefetch and cache lines.
The Flash memory is organized as follows:
• A main memory block divided into sectors.
•
System memory from which the device boots in System memory boot mode
• 512 OTP (one-time programmable) bytes for user data.
•
Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Refer to
2.2.5

Bit banding

The Cortex
each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a
word in the alias region has the same effect as a read-modify-write operation on the
targeted bit in the bit-band region.
In the STM32F446xx devices both the peripheral registers and the SRAM are mapped to a
bit-band region, so that single bit-band write and read operations are allowed. The
operations are only available for Cortex
masters (e.g. DMA).
60/1328
Section 3: Embedded Flash memory interface
®
-M4 with FPU memory map includes two bit-band regions. These regions map
®
-M4 with FPU accesses, and not from other bus
RM0390 Rev 4
Section 5.1.2: Battery backup
in the SYSCFG
for more details.
RM0390