ST STM32WL5 Series Manuals

Manuals and User Guides for ST STM32WL5 Series. We have 2 ST STM32WL5 Series manuals available for free PDF download: Reference Manual

ST STM32WL5 Series Reference Manual (1461 pages)

Advanced Arm-based 32-bit MCUs with sub-GHz radio solution

Brand: ST | Category: Microcontrollers | Size: 17 MB

Sub-Ghz Radio Generic Synchronization Word Control Register
1
Table of Contents
2
Sub-Ghz Radio Generic Synchronization Word Control Register
2
SYSCFG External Interrupt Configuration Register
3
Documentation Conventions

58
- General Information
  58
- List of Abbreviations for Registers
  58
- Glossary
  59
- Availability of Peripherals
  59
Memory and Bus Architecture

60
- System Architecture
  60
  - S0: CPU1 I-Bus
    61
  - S1: CPU1 D-Bus
    61
  - S2: CPU1 S-Bus
    61
  - S3: CPU2 S-Bus
    61
  - Figure 1. System Architecture
    61
  - S4, S5: DMA-Bus
    62
- Boot Configuration
  62
- Table 1. Device Boot Mode
  62
- CPU2 Boot
  64
- SRAM Erase
  65
- Memory Protection
  65
- Table 2. SRAM Erase Conditions
  65
- Figure 2. Memory Protection Example
  67
- Table 3. Memory Security and Privilege Access
  68
- Memory Organization
  70
Global Security Controller (GTZC)

77
Embedded Flash Memory (FLASH)

97
Sub-Ghz Radio (SUBGHZ)

154
Power Control (PWR)

219
- Power Supplies
  219
  - Figure 18. Power Supply Overview
    220
  - Figure 19. Supply Configurations
    221
  - Independent Analog Peripherals Supply
    222
  - Battery Backup Domain
    223
  - Dynamic Voltage Scaling Management
    224
  - Voltage Regulator
    224
- Power Supply Supervisor
  225
  - Power-On Reset (Por)/Power-Down Reset (PDR)
    225
    
    Brownout Reset (BOR)
    225
  - Programmable Voltage Detector (PVD)
    226
  - Figure 20. Brownout Reset Waveform
    226
  - Peripheral Voltage Monitoring (PVM)
    227
  - Table 43. PVM Features
    227
  - Figure 21. PVD Thresholds
    227
  - Radio End of Life (EOL)
    228
- Radio Busy Management
  228
- Figure 22. EOL Thresholds
  228
- Figure 23. Radio Busy Management
  229
- CPU2 Boot
  230
- Figure 24. CPU2 Boot Options
  231
- Low-Power Modes
  232
  - Figure 25. Cpus Low-Power Modes Possible Transitions
    235
  - Table 44. Low-Power Mode Summary
    236
  - Table 45. Functionalities Depending on System Operating Mode
    237
  - Table 46. MCU and Sub-Ghz Radio Operating Modes
    239
  - Low-Power Run Mode (Lprun)
    240
  - Run Mode
    240
  - Enter Low-Power Mode
    241
  - Exit Low-Power Mode
    241
  - Table 47. Lprun
    241
  - Sleep Mode
    243
  - Table 48. CPU Wakeup Versus System Operating Mode
    243
  - Low-Power Sleep Mode (Lpsleep)
    244
  - Table 49. Sleep Mode
    244
  - Stop 0 Mode
    245
  - Table 50. Lpsleep
    245
  - Stop 1 Mode
    247
  - Table 51. Stop 0 Mode
    247
  - Stop 2 Mode
    248
  - Table 52. Stop 1 Mode
    248
  - Standby Mode
    250
  - Table 53. Stop 2 Mode
    250
  - Shutdown Mode
    252
  - Table 54. Standby Mode
    252
  - Auto-Wakeup from Low-Power Mode
    253
  - Table 55. Shutdown Mode
    253
- PWR Registers
  254
Reset and Clock Control (RCC)

277
Hardware Semaphore (HSEM)

365
- Introduction
  365
- Main Features
  365
- Functional Description
  366
  - HSEM Block Diagram
    366
  - HSEM Internal Signals
    366
  - HSEM Lock Procedures
    366
  - Table 64. HSEM Internal Input/Output Signals
    366
  - Figure 33. HSEM Block Diagram
    366
  - Figure 34. Procedure State Diagram
    367
  - HSEM Write/Read/Read Lock Register Address
    368
  - HSEM Unlock Procedures
    368
  - HSEM COREID Semaphore Clear
    369
  - HSEM Interrupts
    369
  - Figure 35. Interrupt State Diagram
    370
  - AHB Bus Master ID Verification
    371
  - Table 65. Authorized AHB Bus Master Ids
    371
- HSEM Registers
  372
Inter-Processor Communication Controller (IPCC)

379
General-Purpose I/Os (GPIO)

393
System Configuration Controller (SYSCFG)

428
- SYSCFG Main Features
  428
- SYSCFG Registers
  428
Peripherals Interconnect Matrix

446
Direct Memory Access Controller (DMA)

454
- Introduction
  454
- DMA Main Features
  454
- DMA Implementation
  455
  - DMA1 and DMA2
    455
  - DMA Request Mapping
    455
  - Table 77. DMA1 and DMA2 Implementation
    455
- DMA Functional Description
  456
  - DMA Block Diagram
    456
  - Figure 49. DMA Block Diagram
    456
  - DMA Pins and Internal Signals
    457
  - DMA Transfers
    457
  - Table 78. DMA Internal Input/Output Signals
    457
  - DMA Arbitration
    458
  - DMA Channels
    459
  - DMA Data Width, Alignment and Endianness
    464
  - Table 79. Programmable Data Width and Endian Behavior (When PINC = MINC = 1)
    464
  - DMA Error Management
    465
- DMA Interrupts
  466
- DMA Registers
  466

ST STM32WL5 Series Reference Manual (1454 pages)

Advanced Arm-based 32-bit MCUs with sub-GHz radio solution

Brand: ST | Category: Microcontrollers | Size: 29 MB

ST Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More ST Manuals

ST STM32WL5 Series Manuals

ST STM32WL5 Series Reference Manual (1461 pages)

Table of Contents

Documentation Conventions

Memory and Bus Architecture

Global Security Controller (GTZC)

Embedded Flash Memory (FLASH)

Sub-Ghz Radio (SUBGHZ)

Power Control (PWR)

Reset and Clock Control (RCC)

Hardware Semaphore (HSEM)

Inter-Processor Communication Controller (IPCC)

General-Purpose I/Os (GPIO)

System Configuration Controller (SYSCFG)

Peripherals Interconnect Matrix

Direct Memory Access Controller (DMA)

ST STM32WL5 Series Reference Manual (1454 pages)

Table of Contents

Table of Contents

List of Tables

Related Products

ST Categories