User Manuals: ST STM32F410 Microcontroller

Manuals and User Guides for ST STM32F410 Microcontroller. We have 1 ST STM32F410 Microcontroller manual available for free PDF download: Reference Manual

ST STM32F410 Reference Manual (771 pages)

Advanced Arm-based 32-bit MCUs

Brand: ST | Category: Microcontrollers | Size: 9 MB

Table of Contents
2
SYSCFG External Interrupt Configuration Register
4
Documentation Conventions

34
- General Information
  34
- List of Abbreviations for Registers
  34
- Glossary
  35
- Availability of Peripherals
  35
System and Memory Overview

36
- System Architecture
  36
  - Figure 1. System Architecture
    36
  - AHB/APB Bridges (APB)
    37
  - Busmatrix
    37
  - D-Bus
    37
  - DMA Memory Bus
    37
  - DMA Peripheral Bus
    37
  - I-Bus
    37
  - S-Bus
    37
- Memory Organization
  38
- Embedded SRAM
  41
- Flash Memory Overview
  41
- Bit Banding
  42
- Boot Configuration
  43
- Table 2. Boot Modes
  43
- Table 3. Embedded Bootloader Interfaces
  43
- Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in STM32F410
  44
Embedded Flash Memory Interface

45
Power Controller (PWR)

69
Reset and Clock Control (RCC)

91
General-Purpose I/Os (GPIO)

135
System Configuration Controller (SYSCFG)

155
- I/O Compensation Cell
  155
- SYSCFG Registers
  155
Direct Memory Access Controller (DMA)

162
- DMA Introduction
  162
- DMA Main Features
  162
- DMA Functional Description
  164
  - DMA Block Diagram
    164
  - DMA Overview
    164
  - Figure 22. DMA Block Diagram
    164
  - DMA Transactions
    165
  - Figure 23. System Implementation of the Two DMA Controllers
    165
  - Channel Selection
    166
  - Table 29. DMA1 Request Mapping
    166
  - Figure 24. Channel Selection
    166
  - Arbiter
    167
  - DMA Streams
    167
  - Table 30. DMA2 Request Mapping
    167
  - Source, Destination and Transfer Modes
    168
  - Table 31. Source and Destination Address
    168
  - Figure 25. Peripheral-To-Memory Mode
    169
  - Figure 26. Memory-To-Peripheral Mode
    170
  - Pointer Incrementation
    171
  - Figure 27. Memory-To-Memory Mode
    171
  - Circular Mode
    172
  - Double-Buffer Mode
    172
  - Programmable Data Width, Packing/Unpacking, Endianness
    173
  - Table 32. Source and Destination Address Registers in Double-Buffer Mode (DBM = 1)
    173
  - Table 33. Packing/Unpacking and Endian Behavior (Bit PINC = MINC = 1)
    174
  - Table 34. Restriction on NDT Versus PSIZE and MSIZE
    174
  - Single and Burst Transfers
    175
  - Fifo
    175
  - Figure 28. FIFO Structure
    175
  - Table 35. FIFO Threshold Configurations
    176
  - DMA Transfer Completion
    178
  - DMA Transfer Suspension
    179
  - Flow Controller
    179
  - Summary of the Possible DMA Configurations
    180
  - Table 36. Possible DMA Configurations
    180
  - Stream Configuration Procedure
    181
  - Error Management
    182
- DMA Interrupts
  183
- Table 37. DMA Interrupt Requests
  183
- DMA Registers
  184
Interrupts and Events

198
CRC Calculation Unit

211
- CRC Introduction
  211
- CRC Main Features
  211
- CRC Functional Description
  211
- Figure 31. CRC Calculation Unit Block Diagram
  211
- CRC Registers
  212
  - Data Register (CRC_DR)
    212
  - Independent Data Register (CRC_IDR)
    213
  - Control Register (CRC_CR)
    213
  - CRC Register Map
    214
  - Table 41. CRC Calculation Unit Register Map and Reset Values
    214
Analog-To-Digital Converter (ADC)

215
- ADC Introduction
  215
- ADC Main Features
  215
- ADC Functional Description
  215
  - Figure 32. Single ADC Block Diagram
    216
  - ADC Clock
    217
  - ADC On-Off Control
    217
  - Channel Selection
    217
  - Table 42. ADC Pins
    217
  - Continuous Conversion Mode
    218
  - Single Conversion Mode
    218
  - Analog Watchdog
    219
  - Figure 33. Timing Diagram
    219
  - Figure 34. Analog Watchdog's Guarded Area
    219
  - Timing Diagram
    219
  - Injected Channel Management
    220
    
    Table 43. Analog Watchdog Channel Selection
    220
    
    Discontinuous Mode
    221
    
    Figure 35. Injected Conversion Latency
    221
  - Scan Mode
    220
  - Data Alignment
    222
  - Channel-Wise Programmable Sampling Time
    223
  - Figure 36. Right Alignment of 12-Bit Data
    223
  - Figure 37. Left Alignment of 12-Bit Data
    223
  - Figure 38. Left Alignment of 6-Bit Data
    223
  - Conversion on External Trigger and Trigger Polarity
    224
  - Table 44. Configuring the Trigger Polarity
    224
  - Table 45. External Trigger for Regular Channels
    224
  - Data Management
    225
    
    Using the DMA
    225
    
    Table 46. External Trigger for Injected Channels
    225
    
    Managing a Sequence of Conversions Without Using the DMA
    226
    
    Conversions Without DMA and Without Overrun Detection
    226
  - Fast Conversion Mode
    225
  - Temperature Sensor
    226
  - Figure 39. Temperature Sensor and VREFINT Channel Block Diagram
    227
  - ADC Interrupts
    228
  - Battery Charge Monitoring
    228
  - Table 47. ADC Interrupts
    228
  - ADC Registers
    229
    
    ADC Status Register (ADC_SR)
    229
    
    ADC Control Register 1 (ADC_CR1)
    230
    
    ADC Control Register 2 (ADC_CR2)
    232
    
    ADC Sample Time Register 1 (ADC_SMPR1)
    234
    
    ADC Sample Time Register 2 (ADC_SMPR2)
    234
    
    ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
    235
    
    ADC Watchdog Higher Threshold Register (ADC_HTR)
    235
    
    ADC Watchdog Lower Threshold Register (ADC_LTR)
    235
    
    ADC Regular Sequence Register 1 (ADC_SQR1)
    236
    
    ADC Regular Sequence Register 2 (ADC_SQR2)
    237
    
    ADC Regular Sequence Register 3 (ADC_SQR3)
    237
    
    ADC Injected Sequence Register (ADC_JSQR)
    238
    
    ADC Injected Data Register X (Adc_Jdrx) (X= 1
    238
    
    ADC Regular Data Register (ADC_DR)
    239
    
    ADC Common Status Register (ADC_CSR)
    239
    
    ADC Common Control Register (ADC_CCR)
    240
    
    11.12.17 ADC Register Map
    241
    
    Table 48. ADC Global Register Map
    241
    
    Table 49. ADC Register Map and Reset Values
    241
    
    Table 50. ADC Register Map and Reset Values (Common ADC Registers)
    242
Digital-To-Analog Converter (DAC)

243
True Random Number Generator (RNG)

257
- Introduction
  257
- RNG Main Features
  257
- RNG Functional Description
  258
  - RNG Block Diagram
    258
  - RNG Internal Signals
    258
  - Table 54. RNG Internal Input/Output Signals
    258
  - Figure 47. RNG Block Diagram
    258
  - Random Number Generation
    259
  - Figure 48. Entropy Source Model
    259
  - RNG Initialization
    261
  - RNG Operation
    261
  - RNG Clocking
    262
  - Error Management
    262
- RNG Low-Power Usage
  263
- RNG Interrupts
  263
- RNG Processing Time
  263
- Table 55. RNG Interrupt Requests
  263
- Entropy Source Validation
  264
  - Introduction
    264
  - Validation Conditions
    264
- RNG Registers
  265
  - RNG Control Register (RNG_CR)
    265
  - RNG Status Register (RNG_SR)
    266
  - RNG Data Register (RNG_DR)
    267
  - RNG Register Map
    268
  - Table 56. RNG Register Map and Reset Map
    268
Advanced-Control Timers (TIM1)

269
General-Purpose Timers (TIM5)

340
General-Purpose Timers (TIM9 and TIM11)

390
Basic Timers (TIM6)

437
Low-Power Timer (LPTIM)

450
- Introduction
  450
- LPTIM Main Features
  450
- LPTIM Implementation
  450
- Table 71. STM32F410 LPTIM Features
  450
- LPTIM Functional Description
  451
  - LPTIM Block Diagram
    451
  - LPTIM Trigger Mapping
    451
  - Table 72. LPTIM1 External Trigger Connection
    451
  - Figure 166. Low-Power Timer Block Diagram
    451
  - LPTIM Input1 Multiplexing
    452
  - LPTIM Reset and Clocks
    452
  - Glitch Filter
    452
  - Prescaler
    453
  - Table 73. Prescaler Division Ratios
    453
  - Figure 167. Glitch Filter Timing Diagram
    453
  - Trigger Multiplexer
    454
  - Operating Mode
    454
  - Figure 168. LPTIM Output Waveform, Single Counting Mode Configuration
    455
  - Figure 169. LPTIM Output Waveform, Single Counting Mode Configuration
    455
  - Timeout Function
    456
  - Waveform Generation
    456
  - Figure 170. LPTIM Output Waveform, Continuous Counting Mode Configuration
    456
  - Register Update
    457
  - Figure 171. Waveform Generation
    457
  - Counter Mode
    458
  - Timer Enable
    458
  - Encoder Mode
    459
  - Table 74. Encoder Counting Scenarios
    459
  - Debug Mode
    460
- LPTIM Low-Power Modes
  460
- Table 75. Effect of Low-Power Modes on the LPTIM
  460
- Figure 172. Encoder Mode Counting Sequence
  460
- LPTIM Interrupts
  461
- LPTIM Registers
  461
Window Watchdog (WWDG)

473
- WWDG Introduction
  473
- WWDG Main Features
  473
- WWDG Functional Description
  473
- Figure 173. Watchdog Block Diagram
  474
- How to Program the Watchdog Timeout
  475
- Figure 174. Window Watchdog Timing Diagram
  475
- Debug Mode
  476
- WWDG Registers
  477
  - Control Register (WWDG_CR)
    477
  - Configuration Register (WWDG_CFR)
    478
  - Status Register (WWDG_SR)
    478
  - WWDG Register Map
    479
  - Table 78. WWDG Register Map and Reset Values
    479
Independent Watchdog (IWDG)

480
- IWDG Introduction
  480
- IWDG Main Features
  480
- IWDG Functional Description
  480
  - Hardware Watchdog
    480
  - Register Access Protection
    480
  - Debug Mode
    481
  - Table 79. Min/Max IWDG Timeout Period at 32 Khz (LSI)
    481
  - Figure 175. Independent Watchdog Block Diagram
    481
- IWDG Registers
  482
  - Key Register (IWDG_KR)
    482
  - Prescaler Register (IWDG_PR)
    483
  - Reload Register (IWDG_RLR)
    484
  - Status Register (IWDG_SR)
    484
  - IWDG Register Map
    485
  - Table 80. IWDG Register Map and Reset Values
    485
Real-Time Clock (RTC)

486
- Introduction
  486
- RTC Main Features
  486
- Figure 176. RTC Block Diagram
  487
- RTC Functional Description
  488
  - Clock and Prescalers
    488
  - Real-Time Clock and Calendar
    488
  - Programmable Alarms
    489
  - Periodic Auto-Wakeup
    489
  - RTC Initialization and Configuration
    490
  - Reading the Calendar
    492
  - Resetting the RTC
    493
  - RTC Synchronization
    493
  - RTC Reference Clock Detection
    494
  - RTC Coarse Digital Calibration
    494
  - RTC Smooth Digital Calibration
    495
  - Timestamp Function
    497
  - Tamper Detection
    498
  - Calibration Clock Output
    499
  - Alarm Output
    500
- RTC and Low Power Modes
  500
- Table 81. Effect of Low Power Modes on RTC
  500
- RTC Interrupts
  501
- Table 82. Interrupt Control Bits
  501
- RTC Registers
  502
Fast-Mode Plus Inter-Integrated Circuit (FMPI2C) Interface

524
Inter-Integrated Circuit (I 2 C) Interface

592
- I 2 C Introduction
  592
- I 2 C Main Features
  593
- C Functional Description
  594
  - Mode Selection
    594
  - Figure 207. I2C Bus Protocol
    594
  - I2C Slave Mode
    595
  - Figure 208. I2C Block Diagram
    595
  - Figure 209. Transfer Sequence Diagram for Slave Transmitter
    597
  - I2C Master Mode
    598
  - Figure 210. Transfer Sequence Diagram for Slave Receiver
    598
  - Figure 211. Transfer Sequence Diagram for Master Transmitter
    601
  - Figure 212. Transfer Sequence Diagram for Master Receiver
    603
  - Error Conditions
    604
  - Programmable Noise Filter
    605
  - Table 101. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)
    605
  - SDA/SCL Line Control
    606
  - Smbus
    606
  - Table 102. Smbus Vs. I2C
    607
  - DMA Requests
    609
  - Packet Error Checking
    610
- I 2 C Interrupts
  611
- Table 103. I2C Interrupt Requests
  611
- Figure 213. I2C Interrupt Mapping Diagram
  612
- I 2 C Debug Mode
  613
- I 2 C Registers
  613
  - C Control Register 1 (I2C_CR1)
    613
  - I 2 C Control Register 2 (I2C_CR2)
    615
  - I 2 C Own Address Register 1 (I2C_OAR1)
    617
  - I 2 C Own Address Register 2 (I2C_OAR2)
    617
  - C Data Register (I2C_DR)
    618
  - C Status Register 1 (I2C_SR1)
    618
  - I 2 C Status Register 2 (I2C_SR2)
    622
  - I 2 C Clock Control Register (I2C_CCR)
    623
  - C TRISE Register (I2C_TRISE)
    624
  - I 2 C FLTR Register (I2C_FLTR)
    625
  - I2C Register Map
    626
  - Table 104. I2C Register Map and Reset Values
    626
Universal Synchronous Receiver Transmitter (USART) /Universal Asynchronous Receiver Transmitter (UART)

627
Serial Peripheral Interface/ Inter-IC Sound (SPI/I2S)

680
Debug Support (DBG)

732
- Overview
  732
- Figure 273. Block Diagram of STM32 MCU and Cortex ® -M4 with FPU-Level
  732
- Reference Arm® Documentation
  733
- SWJ Debug Port (Serial Wire and JTAG)
  733
  - Mechanism to Select the JTAG-DP or the SW-DP
    734
- Pinout and Debug Port Pins
  734
- JTAG TAP Connection
  737
- Figure 275. JTAG TAP Connections
  738
- ID Codes and Locking Mechanism
  739
  - MCU Device ID Code
    739
  - Boundary Scan TAP
    739
  - Cortex ® -M4 with FPU TAP
    739
  - Cortex ® -M4 with FPU JEDEC-106 ID Code
    740
- JTAG Debug Port
  740
- Table 131. JTAG Debug Port Data Registers
  740
- Table 132. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
  741
- SW Debug Port
  742
  - SW Protocol Introduction
    742
  - SW Protocol Sequence
    742
  - Table 133. Packet Request (8-Bits)
    742
  - SW-DP State Machine (Reset, Idle States, ID Code)
    743
  - DP and AP Read/Write Accesses
    743
  - Table 134. ACK Response (3 Bits)
    743
  - Table 135. DATA Transfer (33 Bits)
    743
  - SW-DP Registers
    744
  - Table 136. SW-DP Registers
    744
  - SW-AP Registers
    745
- AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP
  745
- Table 137. Cortex -M4 with FPU AHB-AP Registers
  745
- Core Debug
  746
- Table 138. Core Debug Registers
  746
- Capability of the Debugger Host to Connect under System Reset
  747
- FPB (Flash Patch Breakpoint)
  747
- DWT (Data Watchpoint Trigger)
  748
- ITM (Instrumentation Trace Macrocell)
  748
- ETM (Embedded Trace Macrocell)
  750
  - General Description
    750
  - Signal Protocol, Packet Types
    750
  - Main ETM Registers
    750
  - Configuration Example
    751
- MCU Debug Component (DBGMCU)
  751
- TPIU (Trace Port Interface Unit)
  756
  - Introduction
    756
  - Figure 276. TPIU Block Diagram
    756
  - TRACE Pin Assignment
    757
  - Table 141. Asynchronous TRACE Pin Assignment
    757
  - Table 142. Synchronous TRACE Pin Assignment
    757
  - TPUI Formatter
    758
  - Table 143. Flexible TRACE Pin Assignment
    758
  - TPUI Frame Synchronization Packets
    759
  - Transmission of the Synchronization Frame Packet
    759
  - Synchronous Mode
    759
  - Asynchronous Mode
    760
  - TRACECLKIN Connection
    760
  - TPIU Registers
    760
  - Table 144. Important TPIU Registers
    760
  - 26.17.10 Example of Configuration
    761
- DBG Register Map
  762
- Table 145. DBG Register Map and Reset Values
  762
Device Electronic Signature

763
- Unique Device ID Register (96 Bits)
  763
- Flash Size
  764
- Package Data Register
  764
Revision History

765
- Table 146. Document Revision History
  765

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Motherboard Computer Hardware Microcontrollers Control Unit Controller

More ST Manuals

User Manuals: ST STM32F410 Microcontroller

ST STM32F410 Reference Manual (771 pages)

Table of Contents

Documentation Conventions

System and Memory Overview

Embedded Flash Memory Interface

Power Controller (PWR)

Reset and Clock Control (RCC)

General-Purpose I/Os (GPIO)

System Configuration Controller (SYSCFG)

Direct Memory Access Controller (DMA)

Interrupts and Events

CRC Calculation Unit

Analog-To-Digital Converter (ADC)

Digital-To-Analog Converter (DAC)

True Random Number Generator (RNG)

Advanced-Control Timers (TIM1)

General-Purpose Timers (TIM5)

General-Purpose Timers (TIM9 and TIM11)

Basic Timers (TIM6)

Low-Power Timer (LPTIM)

Window Watchdog (WWDG)

Independent Watchdog (IWDG)

Real-Time Clock (RTC)

Fast-Mode Plus Inter-Integrated Circuit (FMPI2C) Interface

Inter-Integrated Circuit (I 2 C) Interface

Universal Synchronous Receiver Transmitter (USART) /Universal Asynchronous Receiver Transmitter (UART)

Serial Peripheral Interface/ Inter-IC Sound (SPI/I2S)

Debug Support (DBG)

Device Electronic Signature

Revision History

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