Cpu1 Bit Banding - ST STM32WL5 Series Reference Manual

RM0453
Table 4. Memory map and peripheral register boundary addresses (continued)
Bus Boundary address
0x1FFF 7800 - 0x1FFF 7FFF
0x1FFF 7400 - 0x1FFF 77FF
AHB3
0x1FFF 7000 - 0x1FFF 73FF
0x1FFF 0000 - 0x1FFF 6FFF
- 0x1000 8000 - 0x1FFE FFFF
AHB3 0x1000 0000 - 0x1000 7FFF
- 0x0804 0000 - 0x0FFF FFFF
AHB3 0x0800 0000 - 0x0803 FFFF
- 0x0004 0000 - 0x07FF FFFF
BOOT
0x0000 0000 - 0x0003 FFFF
(2)
1. This address corresponds to the maximum Flash memory. For products with smaller Flash size (128 and 64 Kbytes), the
end address is lower.
2. Bus depends on the selected CPUn boot area.
2.6.3

CPU1 bit banding

The CPU1 map includes two bit-band regions. These regions map each word in an alias
region of memory to a bit in a bit-band region of memory. Writing to a word in the alias
region has the same effect as a read-modify-write operation on the targeted bit in the bit-
band region.
The AHB1, APB1, APB2 peripheral registers and the SRAM1 and SRAM2 are mapped to a
bit-band region, so that single bit-band write and read operations are allowed. The
operations are only available for CPU1 accesses and not form other bus masters (such as
DMA).
The peripheral bit-band alias is located from address 0x4200 0000 to 0x425F FFFF.
The SRAM bit-band alias is located from address 0x2200 0000 to 0x221F FFFF.
A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region.
The mapping formula is the following:
bit_word_addr = bit_band_base + (byte_offset * 32) + (bit_number * 4)
where:
• bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.
•
bit_band_base is the starting address of the alias region.
•
byte_offset is the number of the byte in the bit_band region that contains the targeted
bit.
•
bit_number is the bit position (0-7) of the targeted bit.
Size
Peripheral
(bytes)
2 K Flash user options
1 K Flash Engi
1 K Flash OTP
Flash RSS and
28 K
bootloader
- Reserved
SRAM2 (CPU1
32 K
only)
- Reserved
(1)
256 K User Flash
- Reserved
256 K CPUn boot area
RM0453 Rev 1
Peripheral register map
Section 4.10.21: FLASH register map
-
-
-
-
-
-
-
-
-
75/1461
76