Bit Banding; Embedded Flash Memory - ST STM32F100 Series Reference Manual

RM0041
2.3.2

Bit banding

The Cortex
in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the
alias region has the same effect as a read-modify-write operation on the targeted bit in the
bit-band region.
In the STM32F100xx, both peripheral registers and SRAM are mapped in a bit-band region.
This allows single bit-band write and read operations to be performed.
A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region. The mapping formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)
where:
bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit
bit_band_base is the starting address of the alias region
byte_offset is the number of the byte in the bit-band region that contains the targeted
bit
bit_number is the bit position (0-7) of the targeted bit
Example:
The following example shows how to map bit 2 of the byte located at SRAM address
0x2000 0300 in the alias region:
0x2200 6008 = 0x2200 0000 + (0x300*32) + (2*4).
Writing to address 0x2200 6008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM address 0x2000 0300.
Reading address 0x2200 6008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM
address 0x2000 0300 (0x01: bit set; 0x00: bit cleared).
For more information on bit-banding, refer to the Cortex
2.3.3

Embedded flash memory

The high-performance flash memory module has the following key features:
• Density of up to 512 Kbytes
•
Memory organization: the flash memory is organized as a main block and an
information block:
–
–
®
-M3 memory map includes two bit-band regions. These regions map each word
Main memory block of size:
up to 8 Kbit × 32 bits divided into 32 pages of 1 Kbyte each for low-density value
line devices (see Table
up to 32 Kbit × 32 bits divided into 128 pages of 1 Kbyte each for medium-density
value line devices (see
up to 128 Kbit × 32 bits divided into 256 pages of 2 Kbyte each for high-density
value line devices (see
Information block of size:
516 × 32 bits for low, medium and high-density value line devices (see
Table 4 and Table 5)
3)
Table 4)
Table 5)
RM0041 Rev 6
Memory and bus architecture
®
-M3 Technical Reference Manual.
Table 3,
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