Embedded Sram; Flash Memory Overview; Bit Banding - ST STM32F423 Reference Manual

2.3

Embedded SRAM

STM32F413/423 devices feature 320 Kbytes of system SRAM.
The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
Read and write operations are performed at CPU speed with 0 wait state.
The embedded SRAM is divided into two blocks:
•
SRAM1 mapped at address 0x2000 0000 and accessible by all AHB masters.
•
SRAM2 mapped at address 0x2004 0000 and accessible by all AHB masters.
The CPU can access the embedded SRAM1, through the System Bus or through the I-
Code/D-Code buses when boot from SRAM1 is selected or when physical remap is
selected (See
To get the max performance on SRAM1 execution, physical remap should be selected (boot
or software selection).
The CPU can access the embedded SRAM2, through the System Bus or through the I-
Code/D-Code buses when SRAM2 is mapped at the address range: 0x1000 0000 to
0x1000 FFFF. To get the max performance on SRAM2 execution, mapping at the address
0x1000 0000 should be selected.
To get the max performance on embedded SRAM, use SRAM1/SRAM2 to execute code via
I-code and SRAM2/SRAM1 to store data
2.4

Flash memory overview

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms. It accelerates code execution with a system of instruction
prefetch and cache lines.
The Flash memory is organized as follows:
•
A main memory block divided into sectors.
•
System memory from which the device boots in System memory boot mode
•
512 OTP (one-time programmable) bytes for user data.
•
Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Refer to
2.5

Bit banding

The Cortex
each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a
word in the alias region has the same effect as a read-modify-write operation on the
targeted bit in the bit-band region.
In the STM32F4x3xx devices both the peripheral registers and the SRAM1 are mapped to a
bit-band region, so that single bit-band write and read operations are allowed. The
operations are only available for Cortex
masters (e.g. DMA).
62/1324
Section 8.2.1: SYSCFG memory remap register
Section 3: Embedded Flash memory interface
®
-M4 with FPU memory map includes two bit-band regions. These regions map
®
-M4 with FPU accesses, and not from other bus
RM0430 Rev 8
(SYSCFG_MEMRMP)).
for more details.
RM0430