Rcc Clock Configuration Register (Rcc_Cfgr) - ST STM32WL5 Series Reference Manual

Reset and clock control (RCC)
7.4.3

RCC clock configuration register (RCC_CFGR)

Address offset: 0x008
Reset value: 0x0007 0000
(after POR reset and after wakeup from Standby)
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
One or two wait states inserted only if the access occurs during clock source switch.
From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers
values update is ongoing.
31 30 29
Res. MCOPRE[2:0]
rw rw
15 14 13
STOP
Res. PPRE2[2:0]
WUCK
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output selection
Note: This clock output may have some truncated cycles at startup, entering and wakeup
Bits 23:19 Reserved, must be kept at reset value.
302/1461
28 27 26 25
MCOSEL[3:0]
rw rw rw rw
12 11 10 9
PPRE1[2:0]
rw rw rw rw
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO divided by 1
001: MCO divided by 2
010: MCO divided by 4
011: MCO divided by 8
100: MCO divided by 16
Others: not allowed
These bits are set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK system clock selected
0010: MSI clock selected.
0011: HSI16 clock selected.
0100: HSE32 clock selected (after stabilization)
0101: Main PLLRCLK clock selected
0110: LSI clock selected
1000: LSE clock selected
1101: Main PLLPCLK clock selected
1110: Main PLLQCLK clock selected
Others: reserved
from low-power modes, or during MCO clock source switching.
24 23 22
Res. Res.
rw
8 7 6
HPRE[3:0]
rw rw rw
RM0453 Rev 1
21 20 19 18
PPRE
Res. Res. Res.
2F
r
5 4 3 2
SWS[1:0]
rw rw r r
RM0453
17 16
PPRE
HPREF
1F
r r
1 0
SW[1:0]
rw rw