Rcc Clock Configuration Register (Rcc_Cfgr) - ST STM32F207 Series Reference Manual

RM0033
5.3.3

RCC clock configuration register (RCC_CFGR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during a clock source switch.
31 30 29
MCO2 MCO2 PRE[2:0]
rw rw
15 14 13
PPRE2[2:0]
rw rw rw
Bits 31:30 MCO2[1:0]: Microcontroller clock output 2
Set and cleared by software. Clock source selection may generate glitches on MCO2. It is
highly recommended to configure these bits only after reset before enabling the external
oscillators and the PLLs.
00: System clock (SYSCLK) selected
01: PLLI2S clock selected
10: HSE oscillator clock selected
11: PLL clock selected
Bits 27:29 MCO2PRE: MCO2 prescaler
Set and cleared by software to configure the prescaler of the MCO2. Modification of this
prescaler may generate glitches on MCO2. It is highly recommended to change this
prescaler only after reset before enabling the external oscillators and the PLLs.
0xx: no division
100: division by 2
101: division by 3
110: division by 4
111: division by 5
Bits 24:26 MCO1PRE: MCO1 prescaler
Set and cleared by software to configure the prescaler of the MCO1. Modification of this
prescaler may generate glitches on MCO1. It is highly recommended to change this
prescaler only after reset before enabling the external oscillators and the PLL.
0xx: no division
100: division by 2
101: division by 3
110: division by 4
111: division by 5
Bit 23 I2SSRC: I2S clock selection
Set and cleared by software. This bit allows to select the I2S clock source between the
PLLI2S clock and the external clock. It is highly recommended to change this bit only after
reset and before enabling the I2S module.
0: PLLI2S clock used as I2S clock source
1: External clock mapped on the I2S_CKIN pin used as I2S clock source
28 27 26 25
MCO1 PRE[2:0]
rw rw rw rw
12 11 10 9
PPRE1[2:0]
Reserved
rw rw rw
24 23 22
I2SSC
MCO1
R
rw rw rw
8 7 6
HPRE[3:0]
rw rw
RM0033 Rev 9
Reset and clock control (RCC)
21 20 19 18
RTCPRE[4:0]
rw rw rw
5 4 3 2
SWS1 SWS0
rw rw r r
17 16
rw rw
1 0
SW1 SW0
rw rw
99/1381
137