Clock Configuration Register (Rcc_Cfgr) - ST STM32F100 Series Reference Manual

Reset and clock control (RCC)
6.3.2

Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
31 30 29
Reserved
15 14 13
ADC PRE[1:0] PPRE2[2:0]
rw rw rw
Bits 31:27
Bits 26:24 MCO: Microcontroller clock output
Note: This clock output may have some truncated cycles at startup or during MCO clock
Bits 23:22
Bits 21:18 PLLMUL: PLL multiplication factor
Caution: The PLL output frequency must be in the 16-24 MHz range.
82/709
28 27 26 25
MCO[2:0]
rw rw
12 11 10 9
PPRE1[2:0]
rw rw rw rw
Reserved, always read as 0.
Set and cleared by software.
0xx: No clock
100: System clock (SYSCLK) selected
101: HSI clock selected
110: HSE clock selected
111: PLL clock divided by 2 selected
source switching.
Reserved.
These bits are written by software to define the PLL multiplication factor. These bits can be
written only when PLL is disabled.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
24 23 22
Reserved
rw
8 7 6
HPRE[3:0]
rw rw rw
RM0041 Rev 6
21 20 19 18
PLLMUL[3:0]
rw rw rw rw
5 4 3 2
SWS[1:0]
rw rw r r
RM0041
17 16
PLL PLL
XTPRE SRC
rw rw
1 0
SW[1:0]
rw rw