Clock Configuration Register (Rcc_Cfgr) - ST STM32F102 Series Reference Manual

Reset and clock control (RCC)
Bit 16 HSEON External High Speed clock enable
Set and reset by software.
Reset by hardware to stop the external 1-25MHz oscillator when entering in Stop and Standby
mode. This bit can not be reset if the external 1-25 MHz oscillator is used directly or indirectly as
system clock or is selected to become the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0] Internal High Speed clock Calibration
These bits are initialized automatically at startup.
Bits 7:3 HSITRIM[4:0] Internal High Speed clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that
influence the frequency of the internal HSI RC.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ±
1%. The trimming step (F
Bit 2 Reserved, always read as 0.
Bit 1 HSIRDY Internal High Speed clock ready flag
Set by hardware to indicate that internal 8 MHz RC oscillator is stable. This bit needs 6 cycles of the
internal 8 MHz RC oscillator clock to fall down after HSION reset.
0: internal 8 MHz RC oscillator not ready
1: internal 8 MHz RC oscillator ready
Bit 0 HSION Internal High Speed clock enable
Set and reset by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop and Standby mode
or in case of failure of the external 1-25 MHz oscillator used directly or indirectly as system clock.
This bit can not be reset if the internal 8 MHz RC is used directly or indirectly as system clock or is
selected to become the system clock.
0: internal 8 MHz RC oscillator OFF
1: internal 8 MHz RC oscillator ON
6.3.2

Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
31 30 29
Reserved
Res.
15 14 13
ADC PRE[1:0] PPRE2[2:0]
rw rw rw
78/690
) is around 40 kHz between two consecutive HSICAL steps.
hsitrim
28 27 26 25
MCO[2:0]
rw rw
12 11 10 9
PPRE1[2:0]
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24 23 22 21
USB
Res.
PRE
rw Res. rw rw
8 7 6 5
HPRE[3:0]
rw rw rw rw
20 19 18 17
PLL
PLLMUL[3:0]
XTPRE
rw rw rw rw
4 3 2 1
SWS[1:0]
rw r r rw
RM0008
16
PLL
SRC
rw
0
SW[1:0]
rw