Reset And Clock Control (Rcc); Reset; System Reset - ST STM32F100 Series Reference Manual

RM0041
6

Reset and clock control (RCC)

Low-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 16 and 32 Kbytes.
Medium-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 64 and 128 Kbytes.
High-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 256 and 512 Kbytes.
This section applies to all STM32F100xx devices, unless otherwise specified.
6.1

Reset

There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
6.1.1

System reset

A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see
5. Low-power management reset (see
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
Software reset
The SYSRESETREQ bit in Cortex
must be set to force a software reset on the device. Refer to the Cortex
reference manual for more details.
Low-power management reset
There are two ways to generate a low-power management reset:
1. Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting NRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to PM0063.
Section 6.3.10: Control/status register
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-M3 Application Interrupt and Reset Control Register
RM0041 Rev 6
Reset and clock control (RCC)
Software reset)
Low-power management
(RCC_CSR)).
Figure 4).
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