Reset And Clock Control (Rcc) Subsystem; Table 85. Clk_Sm_0; Table 86. Clk_Sm_1; Table 87. Clk_Sm_2 - ST STM32F2 Series User Manual

3.6.19

Reset and clock control (RCC) subsystem

SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations Refer to NVIC_SM_0
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations
SM CODE
Description
UM1845 - Rev 4
Table 85. CLK_SM_0
CLK_SM_0
Periodical read-back of configuration registers
End user
This method must be applied to configuration registers for clock and reset system (refer to RCC
register map).
Detailed information on the implementation of this method can be found in
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 86. CLK_SM_1
CLK_SM_1
Clock security system (CSS)
ST
The clock security system (CSS) detects the loss of HSE clock activity and executes the
corresponding recovery action, such as:
• Switch-off HSE
• Commutation on the HIS
• Generation of related NMI
NMI
Depends on implementation (clock frequency value)
Permanent and Transient
None
CSS protection must be enabled on Clock interrupt register (RCC_CIR) after boot stabilization
Continuous
CLK_SM_0: periodical read-back of configuration registers
CPU_SM_5: external watchdog
It is recommended to carefully read Reference Manual instruction on NMI generation, in order to
correct managing the faulty situation by application software features
Table 87. CLK_SM_2
CLK_SM_2
Independent watchdog
Description of hardware and software diagnostics
Section 3.6.5
UM1845
page 59/108