Reset And Clock Control (Rcc); Reset; System Reset; Power Reset - ST STM32F446 Series Reference Manual

Reset and clock control (RCC)

6 Reset and clock control (RCC)
6.1

Reset

There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
6.1.1

System reset

A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see
5. Low-power management reset (see
Software reset
The reset source can be identified by checking the reset flags in the
status register
The SYSRESETREQ bit in Cortex
Register must be set to force a software reset on the device. Refer to the Cortex
FPU technical reference manual for more details.
Low-power management reset
There are two ways of generating a low-power management reset:
1. Reset generated when entering the Standby mode:
This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes.
In this case, whenever a Standby mode entry sequence is successfully executed, the
device is reset instead of entering the Standby mode.
2. Reset when entering the Stop mode:
This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes.
In this case, whenever a Stop mode entry sequence is successfully executed, the
device is reset instead of entering the Stop mode.
For further information on the user option bytes, refer to
memory
6.1.2

Power reset

A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset
2. When exiting the Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 13)
116/1328
(RCC_CSR).
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Software reset)
Low-power management
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RCC clock control &
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