ST STM32G4 Series Reference Manual page 1532

Advanced arm-based 32-bit mcus

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Real-time clock (RTC)

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ITSF: Internal timestamp flag

Bit 4 TSOVF: Timestamp overflow flag

Bit 3 TSF: Timestamp flag

Bit 2 WUTF: Wakeup timer flag

Bit 1 ALRBF: Alarm B flag

Bit 0 ALRAF: Alarm A flag

The bits of this register are cleared 2 APB clock cycles after setting their corresponding

clear bit in the RTC_SCR register.

RTC masked interrupt status register (RTC_MISR)

Address offset: 0x54

Backup domain reset value: 0x0000 0000

System reset: not affected

This flag is set by hardware when a timestamp on the internal event occurs.

This flag is set by hardware when a timestamp event occurs while TSF is already set.

It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,

an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit

This flag is set by hardware when a timestamp event occurs.

If ITSF flag is set, TSF must be cleared together with ITSF.

This flag is set by hardware when the wakeup auto-reload counter reaches 0.

This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the

alarm B register (RTC_ALRMBR).

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the

alarm A register (RTC_ALRMAR).

RM0440 Rev 1

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