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Functional description
40.5.1.3 Bus clock
The bus clock is used by the control and configuration registers and to generate
synchronous interrupts and DMA requests.
Although there is no specific minimum bus clock frequency
specified, the bus clock frequency must be fast enough (relative
to the bit clock frequency) to ensure that the FIFOs can be
serviced, without generating either a transmitter FIFO underrun
or receiver FIFO overflow condition.
40.5.2 SAI resets
The SAI is asynchronously reset on system reset. The SAI has a software reset and a
FIFO reset.
40.5.2.1 Software reset
The SAI transmitter includes a software reset that resets all transmitter internal logic,
including the bit clock generation, status flags, and FIFO pointers. It does not reset the
configuration registers. The software reset remains asserted until cleared by software.
The SAI receiver includes a software reset that resets all receiver internal logic, including
the bit clock generation, status flags and FIFO pointers. It does not reset the configuration
registers. The software reset remains asserted until cleared by software.
40.5.2.2 FIFO reset
The SAI transmitter includes a FIFO reset that synchronizes the FIFO write pointer to the
same value as the FIFO read pointer. This empties the FIFO contents and is to be used
after TCSR[FEF] is set, and before the FIFO is re-initialized and TCSR[FEF] is cleared.
The FIFO reset is asserted for one cycle only.
The SAI receiver includes a FIFO reset that synchronizes the FIFO read pointer to the
same value as the FIFO write pointer. This empties the FIFO contents and is to be used
after the RCSR[FEF] is set and any remaining data has been read from the FIFO, and
before the RCSR[FEF] is cleared. The FIFO reset is asserted for one cycle only.
814
NOTE
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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