Llwu Flag 2 Register (Llwu_F2) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map/register definition

18.4.7 LLWU Flag 2 register (LLWU_F2)

LLWU_F2 contains the wakeup flags indicating which wakeup source caused the MCU
to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow.
For VLLS, this is the source causing the MCU reset flow.
The external wakeup flags are read-only and clearing a flag is accomplished by a write of
a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if
the associated WUPEx bit is cleared.
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction
Address: 4007_C000h base + 6h offset = 4007_C006h
Bit 7
Read WUF15
Write w1c
Reset
0
Field
7 Wakeup Flag For LLWU_P15
WUF15
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To
clear the flag, write a 1 to WUF15.
0 LLWU_P15 input was not a wakeup source
1 LLWU_P15 input was a wakeup source
6 Wakeup Flag For LLWU_P14
WUF14
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To
clear the flag, write a 1 to WUF14.
0 LLWU_P14 input was not a wakeup source
1 LLWU_P14 input was a wakeup source
5 Wakeup Flag For LLWU_P13
WUF13
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To
clear the flag, write a 1 to WUF13.
0 LLWU_P13 input was not a wakeup source
1 LLWU_P13 input was a wakeup source
276
NOTE
details for more information.
6 5
WUF14 WUF13
w1c w1c
0 0
LLWU_F2 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
4 3
WUF12 WUF11
w1c w1c
0 0
Description
2 1
WUF10 WUF9
w1c w1c
0 0
Freescale Semiconductor, Inc.
0
WUF8
w1c
0